TLK3101_16 Datasheet, PDF (12/28 Pages) Texas Instruments – 2.5 Gbps to 3.125 Gbps TRANSCEIVER

TLK3101
2.5 Gbps to 3.125 Gbps TRANSCEIVER
SCAS649B − AUGUST 2000 − REVISED JANUARY 2008
Terminal Functions
signal
TERMINAL
NAME
NO.
DOUTTXP
60
DOUTTXN
59
DINRXP
54
DINRXN
53
GTX_CLK
8
LCKREFN
25
TXD0
62
TXD1
63
TXD2
64
TXD3
2
TXD4
3
TXD5
4
TXD6
6
TXD7
7
TXD8
10
TXD9
11
TXD10
12
TXD11
14
TXD12
15
TXD13
16
TXD14
17
TXD15
19
RXD0
51
RXD1
50
RXD2
49
RXD3
47
RXD4
46
RXD5
45
RXD6
44
RXD7
42
RXD8
40
RXD9
39
RXD10
37
RXD11
36
RXD12
35
RXD13
34
RXD14
32
RXD15
31
RX_CLK
41
† _{Hi-Z on power up}
‡ _{Internal pullup}
§ _{Low on power up}
TYPE
DESCRIPTION
Output^†
Serial transmit outputs. DOUTTXP and DOUTTXN are differential serial outputs that interface to copper or
an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK value.
DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high and are active when
LOOPEN is low . During power-on-reset these pins are high-impedance.
Input Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a copper
or an optical I/F module.
Input
Input^‡
Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter interface
signals TX_EN, TX_ER and TXD. The frequency range of GTX_CLK is 125 MHz to 156.25 MHz. The
transmitter uses the rising edge of this clock to register the 16-bit input data (TXD) for serialization.
Lock to reference. When LCKREFN is low, the receiver clock is frequency locked to GTX_CLK. This places
the device in a transmit only mode, since the receiver is not tracking the data. When LCKREFN is asserted
low, the receive data bus pins, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS are in a high-impedance
state.
When LCKREFN is deasserted high, the receiver is locked to the received data stream and must receive
valid codes from the synchronization state machine before the transmitter is enabled.
Input
Transmit data bus. These inputs carry the 16-bit parallel data output from a protocol device to the transceiver
for encoding, serialization, and transmission. This 16-bit parallel data is clocked into the transceiver on the
rising edge of GTX_CLK as shown in Figure 10.
Output^† Receive data bus. These outputs carry 16-bit parallel data output from the transceiver to the protocol device,
synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as shown in Figure 12. These pins
are in high-impedance state during power-on reset.
Output^§ Recovered clock. Output clock that is synchronized to RXD, RX_ER, RX_DV/LOS. RX_CLK is the
recovered serial data rate clock divided by 20. RX_CLK is held low during power-on reset.
12
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