DS92LV2421SQX-NOPB Datasheet, PDF (8/50 Pages) Texas Instruments – DS92LV2421/DS92LV2422 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
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DS92LV2422 Deserializer Pin Descriptions (continued)
Pin Name
Pin #
I/O, Type Description⁽¹⁾
Channel-Link II — CML Serial Interface
RIN+
49
I, CML True Input. The input must be AC Coupled with a 0.1 μF capacitor.
RIN-
50
I, CML Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
CMF
51
I, Analog Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
ROUT+
52
O, CML True Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
ROUT-
53
Power and Ground⁽²⁾
O, CML
Inverting Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
VDDL
29
Power Logic Power, 1.8 V ±5%
VDDIR
48
Power Input Power, 1.8 V ±5%
VDDR
43, 55
Power RX High Speed Logic Power, 1.8 V ±5%
VDDSC
4, 58
Power SSCG Power, 1.8 V ±5%
VDDPR
57
Power PLL Power, 1.8 V ±5%
VDDCMLO
54
Power RX High Speed Logic Power, 1.8 V ±5%
VDDIO
GND
13, 24, 38
DAP
Power
Ground
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (V_DDIO)
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
(2) The VDD (V_DDn and V_DDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on
the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
8
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