DS92LV2421SQX-NOPB Datasheet, PDF (25/50 Pages) Texas Instruments – DS92LV2421/DS92LV2422 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421, DS92LV2422
www.ti.com
SNLS321B – MAY 2010 – REVISED APRIL 2013
Ser — Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is latched on. If RFB is High, input data is latched on the Rising
edge of the CLKIN. If RFB is Low, input data is latched on the Falling edge of the CLKIN. Ser and Des maybe
set differently. This feature may be controlled by the external pin or by register.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode for details.
DESERIALIZER Functional Description
The Des converts a single input serial data stream to a wide parallel output bus, and also provides a signal
check for the chipset Built In Self Test (BIST) mode. The device can be configured via external pins and strap
pins or through the optional serial control bus. The Des features enhance signal quality on the link with an
integrated equalizer on the serial input and Channel Link II data encoding which provides randomization,
scrambling, and DC balanacing of the data. The Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and scrambling of the data, the output spread spectrum clock
generation (SSCG) support and output clock and data slew rate select. The Des features power saving features
with a power down mode, and optional LVCMOS (1.8 V) interface compatibility.
Integrated Signal Conditioning Features — Des
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial stream to increase the eye opening to the Des input.
Note this function cannot be seen at the RxIN+/- input but can be observed at the serial test port (ROUT+/-)
enabled via the Serial Bus control registers. The equalization feature may be controlled by the external pin or by
register.
Table 5. Receiver Equalization Configuration Table
EQ3
L
L
L
L
H
H
H
H
X
EQ2
L
L
H
H
L
L
H
H
X
INPUTS
EQ1
L
H
L
H
L
H
L
H
X
EQ0
H
H
H
H
H
H
H
H
L
(1) Default Setting is EQ = Off
EMI Reduction Features
Effect
~1.5 dB
~3 dB
~4.5 dB
~6 dB
~7.5 dB
~9 dB
~10.5 dB
~12 dB
OFF ⁽¹⁾
Des — Output Slew Rate Select (OS_CLKOUT/OS_DATA)
The parallel data outputs and clock outputs of the deserializer feature selectable output slew rates. The slew rate
of the CLKOUT pin is controlled by the strap pin or register OS_CLKOUT, while the data outputs (DO[23:0] and
CO[3:1]) are controlled by the strap pin or register OS_DATA. When OS_CLKOUT/DATA = HIGH, the maxium
slew rate is selected. When the OS_CLKOUT/DATA = LOW, the minimum slew rate is selected. Use the higher
slew rate when driving longer traces or a heavier capacitive load.
Copyright © 2010–2013, Texas Instruments Incorporated
Submit Documentation Feedback
25
Product Folder Links: DS92LV2421 DS92LV2422