DS92LV2421SQX-NOPB Datasheet, PDF (13/50 Pages) Texas Instruments – DS92LV2421/DS92LV2422 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421, DS92LV2422
www.ti.com
SNLS321B – MAY 2010 – REVISED APRIL 2013
Deserializer DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
I_DDZ
I_DDIOZ
Deserializer
Supply Current
Power Down
PDB = 0V, All other LVCMOS
Inputs = 0V
V_DD=
1.89V
All V_DD pins
V_DDIO
=1.89
V
V_DDIO
= 3.6V
V_DDIO
Min Typ
(1)
100
Max Units
(1)
3000 µA
6
50 µA
12 100 µA
Recommended Serializer Timing for CLKIN Requirements
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t_TCP
t_TCIH
Transmit Input CLKIN Period
Transmit Input CLKIN High
Time
10 MHz to 75 MHz, Figure 6
t_TCIL
t_CLKT
SSC_IN
Transmit Input CLKIN Low Time
CLKIN Input Transition Time
CLKIN Input – Spread Spectrum fmod
at 75 MHz
fdev
(1) Specification is verified by design and is not tested in production.
Min ⁽¹⁾
13.3
0.4T
0.4T
0.5
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
t_LHT
Ser Output Low-to-High
Transition Time, Figure 5
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 0
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 1
t_HLT
Ser Output High-to-Low
Transition Time, Figure 5
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 0
R_L = 100Ω, De-emphasis = disabled,
VODSEL = 1
t_DIS
Input Data - Setup Time,
Figure 6
DI[23:0], CI1, CI2, CI3 to CLKIN
t_DIH
Input Data - Hold Time,
Figure 6
CLKIN to DI[23:0], CI1, CI2, CI3
t_XZD
t_PLD ⁽²⁾
Ser Ouput Active to OFF Delay,
Figure 8
Serializer PLL Lock Time,
Figure 7
R_L = 100Ω
t_SD
Serializer Delay - Latency,
Figure 9
R_L = 100Ω
t_DJIT
Ser Output Total Jitter,
Figure 10
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 75MHz
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 43MHz
R_L = 100Ω, De-Emph = disabled,
RANDOM pattern, CLKIN = 10MHz
Min ⁽¹⁾
2
2
Typ
T
0.5T
0.5T
Max⁽¹⁾ Units
100
ns
0.6T ns
0.6T ns
2.4
ns
35
kHz
±2
%
Typ Max⁽¹⁾ Units
200
ps
200
ps
200
ps
200
ps
ns
ns
8
15
ns
1.4
10
ms
144*T 145*T ns
0.28
UI ⁽³⁾
0.27
UI ⁽³⁾
0.35
UI ⁽³⁾
(1) Specification is verified by design and is not tested in production.
(2) When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data
transfer require tPLD
(3) UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*CLK). The UI scales with clock frequency.
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