DS92LV2421SQX-NOPB Datasheet, PDF (4/50 Pages) Texas Instruments – DS92LV2421/DS92LV2422 10 to 75 MHz, 24-bit Channel Link II Serializer and Deserializer

DS92LV2421, DS92LV2422
SNLS321B – MAY 2010 – REVISED APRIL 2013
www.ti.com
Pin Name
Pin #
LVCMOS Parallel Interface
DI[7:0]
34, 33, 32, 29,
28, 27, 26, 25
DI[15:8]
42, 41, 40, 39,
38, 37, 36, 35
DI[23:16]
2, 1, 48, 47,
46, 45, 44, 43
CI1
5
CI2
3
CI3
4
CLKIN
10
Control and Configuration
PDB
21
VODSEL
24
De-Emph
23
RFB
11
CONFIG
[1:0]
ID[x]
SCL
SDA
13, 12
6
8
9
DS92LV2421 Serializer Pin Descriptions
I/O, Type Description⁽¹⁾
I, LVCMOS Parallel Interface Data Input Pins
w/ pull- For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB.
down
I, LVCMOS Parallel Interface Data Input Pins
w/ pull- For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
down
I, LVCMOS Parallel Interface Data Input Pins
w/ pull- For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB.
down
I, LVCMOS
w/ pull-
down
Control Signal Input
For Display/Video Application: CI1 = Data Enable Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2
transitions per 130 clocks regardless of the Control Signal Filter setting.
I, LVCMOS
w/ pull-
down
Control Signal Input
For Display/Video Application: CI2 = Horizontal Sync Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to 2
transitions per 130 clocks regardless of the Control Signal Filter setting.
I, LVCMOS
w/ pull-
down
Control Signal Input
For Display/Video Application: CI3 = Vertical Sync Input
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is
130 clock cycle wide.
I, LVCMOS Clock Input
w/ pull- Latch/data strobe edge set by RFB pin.
down
I, LVCMOS
w/ pull-
down
Power-down Mode Input
PDB = 1, Ser is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down. When the Ser is in the power-down state, the driver outputs
(DOUT+/-) are both logic high, the PLL is shutdown, IDD is minimized. Control Registers are
RESET.
I, LVCMOS
w/ pull-
down
Differential Driver Output Voltage Select (This is can also be control by I2C register.)
VODSEL = 1, LVDS VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph apps
VODSEL = 0, LVDS VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low
power mode.
I, Analog
w/ pull-up
De-Emphasis Control (This can also be controlled by I2C register access.)
De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
See Table 4.
I, LVCMOS
w/ pull-
down
Clock Input Latch/Data Strobe Edge Select (This can also be controlled by I2C register
access.)
RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
I, LVCMOS
w/ pull-
down
00: Control Signal Filter DISABLED
01: Control Signal Filter ENABLED
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
I, Analog I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 11.
I, LVCMOS
I/O,
LVCMOS
Open Drain
I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to V_DDIO.
I2C Serial Control Bus Data Input / Output - Optional
SDA requires an external pull-up resistor V_DDIO.
(1) 1= HIGH, 0 L= LOW
4
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