DS90CF384AQ_15 Datasheet, PDF (8/18 Pages) Texas Instruments – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz

DS90CF384AQ
SNLS345A – AUGUST 2011 – REVISED APRIL 2013
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
ISI is dependent on interconnect length; may be zero.
Figure 11. Receiver LVDS Input Skew Margin
DS90CF384AQ Pin Descriptions — 56L TSSOP Package
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
I/O No.
Description
I 4 Positive LVDS differentiaI data inputs.
I 4 Negative LVDS differential data inputs.
O 28 TTL level data outputs. This includes: 8 Red, 8 Green, 8 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
I 1 Positive LVDS differential clock input.
I 1 Negative LVDS differential clock input.
O 1 TTL Ievel clock output. The falling edge acts as data strobe.
I 1 TTL level input. When asserted (low input) the receiver outputs are low.
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
I 1 Power supply for PLL.
I 2 Ground pin for PLL.
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
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