DS90CF384AQ_15 Datasheet, PDF (4/18 Pages) Texas Instruments – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz

DS90CF384AQ
SNLS345A – AUGUST 2011 – REVISED APRIL 2013
AC Timing Diagrams
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Figure 2. “Worst Case” Test Pattern
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
Figure 2 and Figure 3 show a falling edge data strobe (TxCLK IN / RxCLK OUT).
Recommended pin to signal mapping. Application may choose to define differently, check compatibility with source.
Figure 3. “16 Grayscale” Test Pattern
Figure 4. Receiver CMOS/TTL Output Load and Transition Times
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