DS90CF384AQ_15 Datasheet, PDF (3/18 Pages) Texas Instruments – +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz

DS90CF384AQ
www.ti.com
SNLS345A – AUGUST 2011 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
RECEIVER SUPPLY CURRENT⁽²⁾
Conditions
Min
ICCRW Receiver Supply Current
Worst Case
C_L = 8 pF, Worst Case
Pattern (Figure 2 and
Figure 4)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
ICCRG Receiver Supply Current,
16 Grayscale
C_L = 8 pF, 16 Grayscale
Pattern (Figure 3 and
Figure 4)
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
ICCRZ Receiver Supply Current
Power Down
Power Down = Low, Receiver Outputs
Stay Low during Power Down Mode
Typ⁽¹⁾ Max
49
65
53
70
81
105
28
30
43
10
55
Units
mA
mA
mA
mA
mA
mA
μA
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground
unless otherwise specified (except V_OD and ΔV _OD).
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 4 )
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 4)
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 10)
f = 25 MHz
1.20
RSPos1 Receiver Input Strobe Position for Bit 1
6.91
RSPos2 Receiver Input Strobe Position for Bit 2
12.62
RSPos3 Receiver Input Strobe Position for Bit 3
18.33
RSPos4 Receiver Input Strobe Position for Bit 4
24.04
RSPos5 Receiver Input Strobe Position for Bit 5
29.75
RSPos6 Receiver Input Strobe Position for Bit 6
35.46
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 10)
f = 65 MHz
0.7
RSPos1 Receiver Input Strobe Position for Bit 1
2.9
RSPos2 Receiver Input Strobe Position for Bit 2
5.1
RSPos3 Receiver Input Strobe Position for Bit 3
7.3
RSPos4 Receiver Input Strobe Position for Bit 4
9.5
RSPos5 Receiver Input Strobe Position for Bit 5
11.7
RSPos6
RSKM
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin⁽¹⁾(Figure 11)
13.9
f = 25 MHz
750
f = 65 MHz
500
RCOP
RxCLK OUT Period (Figure 5)
15
RCOH
RxCLK OUT High Time (Figure 5)
f = 65 MHz
5.0
RCOL
RxCLK OUT Low Time (Figure 5)
5.0
RSRC
RxOUT Setup to RxCLK OUT (Figure 5)
4.5
RHRC
RxOUT Hold to RxCLK OUT (Figure 5)
4.0
RCCD
RxCLK IN to RxCLK OUT Delay @ 25°C, V_CC = 3.3V (Figure 6)
3.5
RPLLS
Receiver Phase Lock Loop Set (Figure 7)
RPDD
Receiver Power Down Delay (Figure 9)
Typ
2
1.8
1.96
7.67
13.38
19.09
24.80
30.51
36.22
1.1
3.3
5.5
7.7
9.9
12.1
14.3
T
7.6
6.3
7.3
6.3
5.0
Max
5
5
2.82
8.53
14.24
19.95
25.66
31.37
37.08
1.4
3.6
5.8
8.0
10.2
12.4
14.6
50
9.0
9.0
7.5
10
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ms
μs
(1) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the
DS90C383B transmitter pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window -
RSPos). The RSKM will change when different transmitters are used. This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: DS90CF384AQ
Submit Documentation Feedback
3