BQ4802YDWRG4 Datasheet, PDF (8/26 Pages) Texas Instruments – PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR

bq4802Y
bq4802LY
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
WRITE CYCLE TIMING DIAGRAMS
Address
CS
tAS
tWC
tAW
tCW
tWP
www.ti.com
tWR1
WE
tDW
tDH1
DIN
Data-In Valid
tWZ
tOW
DOUT
Data Undefined (see Note B)
High-Z
NOTES: A. WE or CS must be held high during address transition.
B. Because I/O may be active (OE low) during the period, data input signals of opposite polarity to the outputs must be applied.
C. If OE is high, the I/O pins remain in a state of high impedance.
Figure 7. Write Cycle No. 1 – WE Controlled
Address
tAS
CS
WE
DIN
tWC
tAW
tCW
tWR2
tWP
tDW
tDH2
Data-In Valid
tWZ
DOUT
Data Undefined (see Note B)
High-Z
NOTES: A. WE or CS must be held high during address transition.
B. Because I/O may be active (OE low) during the period, data input signals of opposite polarity to the outputs must be applied.
C. If OE is high, the I/O pins remain in a state of high impedance.
D. Either tWR1 or tWR2 must be met.
E. Either tDH1 or tDH2 must be met.
Figure 8. Write Cycle No. 2 – CS Controlled
8