BQ4802YDWRG4 Datasheet, PDF (6/26 Pages) Texas Instruments – PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR

bq4802Y
bq4802LY
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
Terminal Functions (Continued)
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TERMINAL
NAME
NO.
WDI
23
WDO
4
WE
27
X1
2(1)
X2
3(1)
I/O
DESCRIPTION
I WDIis a three-level input. If WDI remains either high or low for longer than the watchdog time-out period (1.5-s default),
WDO goes low. WDO remains low until the next transition at WDI. Leaving WDI unconnected disables the watchdog
function. WDI connects to an internal voltage divider between VOUT and VSS, which sets it to mid-supply when left
unconnected.
WDO goes low if WDI remains either high or low longer than the watchdog time-out period. WDO returns high on the
next transition at WDI. WDO remains high if WDI is unconnected.
WE provides the write control for the RTC memory locations.
Crystal connection
FUNCTIONAL BLOCK DIAGRAM
Figure 3 is a block diagram of the bq4802Y/bq4802LY. The following sections describe the bq4802Y/bq4802LY
functional operation including clock interface, data-retention modes, power-on reset timing, watchdog timer
activation, and interrupt generation.
X1
Time-
Base
X2
Oscillator
÷8
÷64
÷64
4
16:1 MUX
Control/Status
Registers
Clock/Calendar and
Alarm Registers
Clock/Calendar
Update
User Buffer
(16 Bytes)
Interrupt
Generator
Watchdog
Transition
Detector
µP Bus
Interface
Power-Fail
Control, Battery
Switchover and
Reset Circuits
A0 – A3 _{DQ0 – DQ7}
CS OE WE
WDI CEIN VCC BC
Figure 3. Block Diagram
6
INT
WDO
RST
VOUT
CEOUT