BQ4802YDWRG4 Datasheet, PDF (13/26 Pages) Texas Instruments – PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR

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Table 3. Clock and Control Register Map
BIT
24/12
ABE
AF
AIE
ALM0–ALM1
BVF
DSE
PF
PIE
PM/AM
PWRF
PWRIE
RS0–RS3
STOP
UTI
WD0–WD2
DESCRIPTION
24- or 12-hour data representation
Alarm interrupt enable in battery-backup mode
Alarm interrupt flag
Alarm interrupt enable
Alarm mask bits
Battery-valid flag
Daylight savings enable
Periodic interrupt flag
Periodic interrupt enable
PM or AM indication
Power-fail interrupt flag
Power-fail interrupt enable
Periodic interrupt rate
Oscillator stop and start
Update transfer inhibit
Watchdog time-out rate
CLOCK MEMORY INTERFACE
The bq4802Y/bq4802LY has the same interface for
clock/calendar and control information as standard
SRAM. To read and write to these locations, the user must
put the bq4802Y/bq4802LY in the proper mode and meet
the timing requirements.
READ MODE
The bq4802Y/bq4802LY is in read mode whenever OE
(output enable) is low and CS (chip select) is low. The
unique address, specified by the four address inputs,
defines which one of the 16 clock/calendar bytes is to be
accessed. The bq4802Y/bq4802LY makes valid data
available at the data I/O pins within t_AA (address access
time). This occurs after the last address input signal is
stable, and providing the CS and OE (output enable)
access times are met. If the CS and OE access times are
not met, valid data is available after the latter of chip select
access time (t_ACS) or output enable access time (t_OE).
CS and OE control the state of the eight three-state data
I/O signals. If the outputs are activated before t_AA, the data
lines are driven to an indeterminate state until t_AA. If the
address inputs are changed while CS and OE remain low,
output data remains valid for t_OH (output data hold time),
but goes indeterminate until the next address access.
WRITE MODE
The bq4802Y/bq4802LY is in write mode whenever WE
and CS are active. The start of a write is referenced from
the latter-occurring falling edge of WE or CS. A write is
terminated by the earlier rising edge of WE or CS. The
addresses must be held valid throughout the cycle. CS or
bq4802Y
bq4802LY
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
WE must return high for a minimum of t_WR2 from CS or
t_WR1 from WE prior to the initiation of another read or write
cycle.
Data-in must be valid t_DW prior to the end of write and
remain valid for t_DH1 or t_DH2 afterward. OE should be kept
high during write cycles to avoid bus contention; although,
if the output bus has been activated by a low on CS and
OE, a low on WE disables the outputs t_WZ after WE falls.
READING THE CLOCK
Once every second, the user-accessible clock/calendar
locations are updated simultaneously from the internal
real-time counters. To prevent reading data in transition,
updates to the bq4802Y/bq4802LY clock registers should
be halted. Updating is halted by setting the update transfer
inhibit (UTI) bit D3 of the control register E. As long as the
UTI bit is 1, updates to user-accessible clock locations are
inhibited. Once the frozen clock information is retrieved by
reading the appropriate clock memory locations, the UTI
bit should be reset to 0 in order to allow updates to occur
from the internal counters. Because the internal counters
are not halted by setting the UTI bit, reading the clock
locations has no effect on clock accuracy. Once the UTI bit
is reset to 0, the internal registers update within one
second the user-accessible registers with the correct time.
A halt command issued during a clock update allows the
update to occur before freezing the data.
SETTING THE CLOCK
The UTI bit must also be used to set the
bq4802Y/bq4802LY clock. Once set, the locations can be
written with the desired information in BCD format.
Resetting the UTI bit to 0 causes the written values to be
transferred to the internal clock counters and allows
updates to the user-accessible registers to resume within
one second.
STOPPING AND STARTING THE CLOCK
OSCILLATOR
The bq4802Y/bq4802LY clock can be programmed to turn
off when the part goes into battery back-up mode by setting
STOP to 0 prior to power down. If the board using the
bq4802Y/bq4802LY is to spend a significant period of time
in storage, the STOP bit can be used to preserve some
battery capacity. STOP set to 1 keeps the clock running
when V_CC drops below V_SO. With V_CC greater than V_SO,
the bq4802Y/bq4802LY clock runs regardless of the state
of STOP.
POWER-DOWN/POWER-UP CYCLE
The bq4802Y/bq4802LY continuously monitors V_CC for
out-of-tolerance. During a power failure, when V_CC falls
below V_PFD, the bq4802Y/bq4802LY write-protects the
clock and storage registers. The power source is switched
to BC when V_CC is less than V_PFD and BC is greater than
V_PFD, or when V_CC is less than V_BC and V_BC is less than
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