BQ4802YDWRG4 Datasheet, PDF (7/26 Pages) Texas Instruments – PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR

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READ CYCLE TIMING DIAGRAMS
Address
tOH
tRC
tAA
bq4802Y
bq4802LY
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
DOUT
Previous Data Valid
Data Valid
NOTES: A. WE is held high for a read cycle.
B. Device is continuously selected: CS = OE = VIL.
Figure 4. Read Cycle No. 1 – Address Access
CS
tRC
tCLZ
tACS
DOUT
High-Z
NOTES: A. WE is held high for a read cycle.
B. Device is continuously selected: CS = OE = VIL.
C. OE = VIL.
Figure 5. Read Cycle No. 2 – CS Access
tRC
Address
tAA
tCHZ
High-Z
OE
tOE
tOLZ
tOHZ
DOUT
High-Z
NOTES: A. WE is held high for a read cycle.
B. CS = VIL.
Figure 6. Read Cycle No. 3 – OE Access
Data Valid
High-Z
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