BQ4802YDWRG4 Datasheet, PDF (15/26 Pages) Texas Instruments – PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR

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bq4802Y
bq4802LY
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
WDI
WDO
t2
RST
t1
t1
t3
Figure 11. Watchdog Time-Out Period and Reset Active Time
Table 4. Watchdog and Reset Timeout Rates
Table 5. Periodic Interrupt Rates
WD2
0
0
0
0
1
1
1
1
WD1
0
0
1
1
0
0
1
1
WD0
0
1
0
1
0
1
0
1
WATCHDOG
TIMEOUT PERIOD
1.50 s
23.4375 ms
46.875 ms
93.750 ms
187.5 ms
375 ms
750 ms
3.0 s
RESET TIMEOUT
PERIOD
0.25 ms
3.9063 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
125 ms
0.5 s
INTERRUPTS
The bq4802Y/bq4802LY allows three individually selected
interrupt events to generate an interrupt request on the INT
pin. These three interrupt events are:
D The periodic interrupt, programmable to occur once
every 30.5 µs to 500 ms.
D The alarm interrupt, programmable to occur once per
second to once per month.
D The power-fail interrupt, which can be enabled to be
asserted when the bq4802Y/bq4802LY detects a
power failure.
An individual interrupt-enable bit in register C, the
interrupts register, enables the periodic, alarm and
power-fail interrupts. When an event occurs, its event flag
bit in the flags register, register D, is set. If the
corresponding event enable bit is also set, then an
interrupt request is generated. Reading the flags register
clears all flag bits and makes INT high impedance. To reset
the flag register, the bq4802Y/bq4802LY addresses must
be held stable at register D for at least 50 ns to avoid
inadvertent resets.
Periodic Interrupt
Bits RS3 – RS0 in the interrupt register program the rate
for the periodic interrupt. The user can interpret the
interrupt in two ways, either by polling the flags register for
PF assertion or by setting PIE so that INT goes active
when the bq4802Y/bq4802LY sets the periodic flag.
Reading the flags register resets the PF bit and returns INT
to the high-impedance state. Table 5 shows the periodic
rates.
REGISTER BITS
PERIODIC
INTERRUPT
RS3
RS2
RS1
RS0
PERIOD
0
0
0
0
NONE
0
0
0
1
30.5175 µs
0
0
1
0
61.035 µs
0
0
1
1
122.070 µs
0
1
0
0
244.141 µs
0
1
0
1
488.281 µs
0
1
1
0
976.5625 µs
0
1
1
1
1.95315 ms
1
0
0
0
3.90625 ms
1
0
0
1
7.8125 ms
1
0
1
0
15.625 ms
1
0
1
1
31.25 ms
1
1
0
0
62.5 ms
1
1
0
1
125 ms
1
1
1
0
250 ms
1
1
1
1
500 ms
ALARM INTERRUPT
Registers 1, 3, 5, and 7 program the real-time clock alarm.
During each update cycle, the bq4802Y/bq4802LY
compares the date, hours, minutes, and seconds in the
clock registers with the corresponding alarm registers. If a
match between all the corresponding bytes is found, the
alarm flag AF in the flags register is set. If the alarm
interrupt is enabled with AIE, an interrupt request is
generated on INT. The alarm condition is cleared by a read
to the flags register. ALM1 – ALM0 in the alarm registers,
mask each alarm compare byte. Setting ALM1 (D7) and
ALM0 (D6) to 1 masks an alarm byte. Alarm byte masking
can be used to select the frequency of the alarm interrupt,
according to Table 6. The alarm interrupt can be made
active while the bq4802Y/bq4802LY is in the battery-
backup mode by setting ABE in the interrupts register.
Normally, the INT pin goes high-impedance during battery
backup. With ABE set, INT is driven low if an alarm
condition occurs and the AIE bit is set.
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