BQ4802YDWRG4 Datasheet, PDF (14/26 Pages) Texas Instruments – PARALLEL REAL-TIME CLOCK WITH CPU SUPERVISOR

bq4802Y
bq4802LY
SLUS464C – AUGUST 2000 – REVISED JUNE 2002
V_PFD. RTC operation and storage data are sustained by a
valid backup energy source. When V_CC is above V_PFD, the
power source is V_CC. Write-protection continues for t_CSR
time after V_CC rises above V_PFD.
An external CMOS static RAM is battery-backed using the
V_OUT and chip enable output pins from the bq4802Y/
bq4802LY. As the voltage input V_CC slews down during a
power failure, the chip enable output, CE_OUT, is forced
inactive independent of the chip enable input CE_IN.
This activity unconditionally write-protects the external
SRAM as V_CC falls below V_PFD. If a memory access is in
progress to the external SRAM during power-fail
detection, that memory cycle continues to completion
before the memory is write-protected. If the memory cycle
is not terminated within time t_WPT, the chip enable output
is unconditionally driven high, write-protecting the
controlled SRAM.
As the supply continues to fall past V_PFD, an internal
switching device forces V_OUT to the external backup
energy source. CE_OUT is held high by the V_OUT energy
source.
During power up, V_OUT is switched back to the main supply
as V_CC rises above the backup cell input voltage sourcing
V_OUT. If V_PFD < V_BC on the bq4802Y/bq4802LY the switch
to the main supply occurs at V_PFD. _CEOUT is held inactive
for time t_CER (200-ms maximum) after the power supply
has reached V_PFD, independent of the CE_IN input, to allow
for processor stabilization.
During power-valid operation, the CE_IN input is passed
through to the CE_OUT output with a propagation delay of
less than 12 ns. Figure 2 shows the hardware hookup for
the external RAM, battery, and crystal.
A primary backup energy source input is provided on the
bq4802Y/bq4802LY. The BC input accepts a 3-V primary
battery, typically some type of lithium chemistry. Since the
bq4802Y/bq4802LY provides for reverse battery charging
protection, no diode or current limiting resistor is needed
in series with the cell. To prevent battery drain when there
is no valid data to retain, V_OUT and CE_OUT are internally
isolated from BC by the initial connection of a battery.
Following the first application of V_CC above V_PFD, this
isolation is broken, and the backup cell provides power to
V_OUT and CE_OUT for the external SRAM. The crystal
should be located as close to X1 and X2 as possible and
meet the specifications in the crystal specifications section
of the electrical characteristics tables. With the specified
crystal, the bq4802Y/bq4802LY RTC is accurate to within
one minute per month at room temperature. In the absence
of a crystal, a 32.768-kHz waveform can be fed into X1 with
X2 grounded. The power source and crystal are integrated
into the SNAPHAT modules.
14
www.ti.com
Power-On Reset
The bq4802Y/bq4802LY provides a power-on reset, which
pulls the RST pin low on power down and remains low on
power up for t_RST after V_CC passes V_PFD. With valid
battery voltage on BC, RST remains valid for V_CC = V_SS.
Push-Button Reset
The bq4802Y/bq4802LY also provides a push-button
override to the reset when the device is not already in a
reset cycle. When the RST pin is released after being
pulled low for 1 µs then the RST stays low for 200 ms
(typical).
WATCHDOG TIMER
The watchdog monitors microprocessor activity through
the watchdog input (WDI). To use the watchdog function,
connect WDI to a bus line or a microprocessor I/O line. If
WDI remains high or low for longer than the watchdog
time-out period (1.5 seconds default), the bq4802Y/
bq4802LY asserts WDO and RST.
Watchdog Input
The bq4802Y/bq4802LY resets the watchdog timer if a
change of state (high-to-low, low-to-high, or a minimum
100 ns pulse) occurs at the watchdog input (WDI) during
the watchdog period. The watchdog time-out is set by
WD0 – WD2 in register B. The bq4802Y/bq4802LY
maintains the watchdog time-out programming through
power cycles. The default state (no valid battery power) of
WD0 – WD2 is 000 or 1.5 s on power up. Table 3 shows
the programmable watchdog time-out rates. The
watchdog time-out period immediately after a reset is
equal to the programmed watchdog time-out.
To disable the watchdog function, leave WDI floating. An
internal resistor network (100-kΩ equivalent impedance at
WDI) biases WDI to approximately 1.6 V. Internal
comparators detect this level and disable the watchdog
timer. When V_CC is below the power-fail threshold, the
bq4802Y/bq4802LY disables the watchdog function and
disconnects WDI from its internal resistor network, thus
making it high impedance.
Watchdog Output
The watchdog output (WDO) remains high if there is a
transition or pulse at WDI during the watchdog timeout
period. The bq4802Y/bq4802LY disables the watchdog
function and WDO is a logic high when V_CC is below the
power fail threshold, battery-backup mode is enabled, or
WDI is an open circuit. In watchdog mode, if no transition
occurs at WDI during the watchdog time-out period, the
bq4802Y/bq4802LY asserts RST for the reset time-out
period t1. WDO goes low and remains low until the next
transition at WDI. If WDI is held high or low indefinitely,
RST generates pulses (t1 seconds wide) every t3
seconds. Figure 11 shows the watchdog timing.