MSP430FR5739-EP_16 Datasheet, PDF (78/95 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR5739-EP
SLVSCN6A – NOVEMBER 2014 – REVISED DECEMBER 2014
www.ti.com
Table 6-13. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
PJ.0/TDO/TB0OUTH/SMCLK/CD6
x
0 PJ.0 (I/O) ⁽²⁾
TDO ⁽³⁾
FUNCTION
CONTROL BITS/ SIGNALS ⁽¹⁾
PJDIR.x PJSEL1.x PJSEL0.x
I: 0; O: 1
0
0
X
X
X
TB0OUTH
SMCLK
0
0
1
1
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7
CD6
1 PJ.1 (I/O) ⁽²⁾
TDI/TCLK ^{(3) (4)}
X
1
1
I: 0; O: 1
0
0
X
X
X
TB1OUTH
MCLK
0
0
1
1
PJ.2/TMS/TB2OUTH/ACLK/CD8
CD7
2 PJ.2 (I/O) ⁽²⁾
TMS ^{(3) (4)}
X
1
1
I: 0; O: 1
0
0
X
X
X
TB2OUTH
ACLK
0
0
1
1
PJ.3/TCK/CD9
CD8
3 PJ.3 (I/O) ⁽²⁾
TCK ^{(3) (4)}
X
1
1
I: 0; O: 1
0
0
X
X
X
CD9
X
1
1
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made by the SYS module or by the Spy-Bi-Wire four-wire
entry sequence. PJSEL1.x and PJSEL0.x have no effect in these cases.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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Input/Output Schematics
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