MSP430FR5739-EP_16 Datasheet, PDF (34/95 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR5739-EP
SLVSCN6A – NOVEMBER 2014 – REVISED DECEMBER 2014
www.ti.com
5 Detailed Description
5.1 Functional Block Diagram
This section shows the functional block diagram for the MSP430FR5739-EP in the RHA package.
PJ.4/XIN PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
PA
PB
P1.x P2.x P3.x P4.x
Clock
System
ACLK
SMCLK
16 KB
(FR5739)
8 KB
(FR5735)
4 KB
(FR5731)
MCLK
FRAM
Memory
Protection
Unit
CPUXV2
and
Working
Registers
MAB
MDB
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
REF
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1×10 I/Os
DMA
3 Channel
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
EEM
(S: 3+1)
JTAG/
SBW
Interface
MPY32
TA0
TB0
TA1
TB1
TB2
(2) Timer_A (3) Timer_B
3 CC
3 CC
Registers Registers
RTC_B
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
eUSCI_A1:
UART,
IrDA, SPI
ADC10_B
10 Bit
200KSPS
Comp_D
16 channels
14 channels
(12 ext/2 int)
5.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator, respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
5.3 Operating Modes
The MSP430 has one active mode and seven software-selectable low-power modes of operation. An
interrupt event can wake up the device from low-power modes LPM0 through LPM4, service the request,
and restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5
and LPM4.5 disable the core supply to minimize power consumption.
The following eight operating modes can be configured by software:
34
Detailed Description
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