TMS320C6654 Datasheet, PDF (77/222 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6654
Fixed and Floating-Point Digital Signal Processor
www.ti.com
SPRS841—March 2012
3.3.13 IPC Acknowledgement (IPCARx) Registers
IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.
The C6654 has only IPCAR0. This register also provides a Source ID facility by which up to 28 different sources of
interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software
convention. The register field descriptions are shown in the following tables. Virtually anything can be a source for
these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space
can write to these registers. The IPC Acknowledgement Register is shown in Figure 3-12 and described in
Table 3-14.
Figure 3-12 IPC Acknowledgement Registers (IPCARx)
31
30
29
28
27
8
7
6
5
4
3
0
SRCC27 SRCC26 SRCC25 SRCC24
SRCC23 – SRCC4
SRCC3 SRCC2 SRCC1 SRCC0
Reserved
RW +0 RW +0 RW +0 RW +0
RW +0 (per bit field)
RW +0 RW +0 RW +0 RW +0
R, +0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
Table 3-14 IPC Acknowledgement Registers (IPCARx) Field Descriptions
Bit Field
31-4 SRCCx
3-0 Reserved
End of Table 3-14
Description
Interrupt source acknowledgement.
Reads return current value of internal register bit.
Writes:
0 = No effect
1 = Clears both SRCCx and the corresponding SRCSx
Reserved
3.3.14 IPC Generation Host (IPCGRH) Register
IPCGRH register is provided to facilitate host DSP interrupt. Operation and use of IPCGRH is the same as
other IPCGR registers. Interrupt output pulse created by IPCGRH is driven on a device pin, host interrupt/event
output (HOUT).
The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles (CPU/6)
followed by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 CPU/6 cycle pulse blocking
window. Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they are beyond 8 CPU/6 cycle
period. The IPC Generation Host Register is shown in Figure 3-13 and described in Table 3-15.
Figure 3-13 IPC Generation Registers (IPCGRH)
31
30
29
28
27
8
7
6
5
4
3
1
0
SRCS27 SRCS26 SRCS25 SRCS24
SRCS23 – SRCS4
SRCS3 SRCS2 SRCS1 SRCS0
Reserved
IPCG
RW +0 RW +0 RW +0 RW +0
RW +0 (per bit field)
RW +0 RW +0 RW +0 RW +0
R, +000
RW +0
Legend: R = Read only; RW = Read/Write; -n = value after reset
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