TMS320C6654 Datasheet, PDF (212/222 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
7.23 Universal Parallel Port (UPP)
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The Universal Parallel Port (UPP) peripheral is a multichannel, high-speed parallel interface with dedicated data
lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters
(ADCs) or digital-to-analog converters (DACs) with up to 16-bit data width (per channel). It may also be
interconnected with field-programmable gate arrays (FPGAs) or other UPP devices to achieve high-speed digital
data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which its individual channels
operate in opposite directions.
The UPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU overhead
during high-speed data transmission. All UPP transactions use the internal DMA to provide data to or retrieve data
from the I/O channels. The DMA controller includes two DMA channels, which typically service separate I/O
channels. The UPP peripheral also supports data interleave mode, in which all DMA resources service a single I/O
channel. In this mode, only one I/O channel may be used.
The features of the UPP include:
• Programmable data width per channel (from 8 bits to 16 bits inclusive)
• Programmable data justification
– Right-justify with 0 extend
– Right-justify with sign extend
– Left-justify with 0 fill
• Supports multiplexing of interleaved data during SDR transmit
• Optional frame START signal with programmable polarity
• Optional data ENABLE signal with programmable polarity
• Optional synchronization WAIT signal with programmable polarity
• Single Data Rate (SDR) or Double data Rate (DDR, interleaved) interface
– Supports multiplexing of interleaved data during SDR transmit
– Supports demultiplexing and multiplexing of interleaved data during DDR transfers
For more information, see the Universal Parallel Port (UPP) for KeyStone Devices User Guide in ‘‘Related
Documentation from Texas Instruments’’ on page 64.
7.23.1 UPP Register Descriptions
Table 7-84 Universal Parallel Port (UPP) Registers (Part 1 of 2)
Byte Address
0x0258 0000
0x0258 0004
0x0258 0008
0x0258 0010
0x0258 0014
0x0258 0018
0x0258 001C
0x0258 0020
0x0258 0024
0x0258 0028
0x0258 002C
0x0258 0030
0x0258 0040
Acronym
UPPID
UPPCR
UPDLB
UPCTL
UPICR
UPIVR
UPTCR
UPISR
UPIER
UPIES
UPIEC
UPEOI
UPID0
Register Description
UPP Peripheral Identification Register
UPP Peripheral Control Register
UPP Digital Loopback Register
UPP Channel Control Register
UPP Interface Configuration Register
UPP Interface Idle Value Register
UPP Threshold Configuration Register
UPP Interrupt Raw Status Register
UPP Interrupt Enabled Status Register
UPP Interrupt Enable Set Register
UPP Interrupt Enable Clear Register
UPP End-of-Interrupt Register
UPP DMA Channel I Descriptor 0 Register
212 Peripheral Information and Electrical Specifications
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