TMS320C6654 Datasheet, PDF (132/222 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
www.ti.com
7.5.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
When a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the DCHANGE status
register. During the GO operation, the PLL controller will change only the divide ratio of the SYSCLKs with the bit
set in DCHANGE. Note that the ALNCTL register determines if that clock also needs to be aligned to other clocks.
The PLLDIV divider ratio change status register is shown in Figure 7-11 and described in Table 7-18.
Figure 7-11 PLLDIV Divider Ratio Change Status Register (DCHANGE)
31
8
7
6
5
4
3
2
1
0
Reserved
SYS8
Reserved
SYS5
Reserved
SYS2
Reserved
R-0
R/W-0
R-0
R/W-0
R-0
R/W-0
R-0
Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value
Table 7-18 PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit
Field
31-8
6-5
Reserved
3-2
0
7
SYS8
4
SYS5
1
SYS2
End of Table 7-18
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Identifies when the SYSCLKn divide ratio has been modified.
0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.
1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.
7.5.2.5 SYSCLK Status Register (SYSTAT)
The SYSCLK status register (SYSTAT) shows the status of SYSCLK[11:1]. SYSTAT is shown in Figure 7-12 and
described in Table 7-19.
Figure 7-12 SYSCLK Status Register (SYSTAT)
31
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
SYS11ON SYS10ON SYS9ON SYS8ON SYS7ON SYS6ON SYS5ON SYS4ON SYS3ON SYS2ON SYS1ON
R-n
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
R-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-19 SYSCLK Status Register (SYSTAT) Field Descriptions
Bit
31-11
10-0
Field
Reserved
SYS[N ⁽¹⁾]ON
End of Table 7-19
Description
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
SYSCLK[N] on status.
0 = SYSCLK[N] is gated.
1 = SYSCLK[N] is on.
1 Where N = 1, 2, 3,....N (Not all these output clocks may be used on a specific device. For more information, see the device-specific data manual)
132 Peripheral Information and Electrical Specifications
Copyright 2012 Texas Instruments Incorporated
TI Confidential—NDA Restrictions