TMS320C6654 Datasheet, PDF (100/222 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
5.1.4 MSM Controller
The MSM configuration for the device is as follows:
• Allows extension of external addresses from 2GB to up to 8GB
• Has built in memory protection features
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For more details on external memory address extension and memory protection features, see the Multicore Shared
Memory Controller (MSMC) for KeyStone Devices User Guide in ‘‘Related Documentation from Texas Instruments’’
on page 64.
5.1.5 L3 Memory
The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement
to block accesses from this portion to the ROM.
5.2 Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2
memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB
each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P, and L2 memory controllers in
the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In
addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct
DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by
other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses. On a
secure device, pages can be restricted to secure access only (default) or opened up for public, non-secure access.
The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify whether
memory pages are locally or globally accessible.
The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection
scheme, see Table 5-1.
Table 5-1
Available Memory Page Protection Schemes
AIDx Bit
Local Bit Description
0
0
No access to memory page is permitted.
0
1
Only direct access by DSP is permitted.
1
0
Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).
1
1
End of Table 5-1
All accesses permitted.
Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac interrupt
controller) service routine. A DSP or DMA access to a page without the proper permissions will:
• Block the access — reads return 0, writes are ignored
• Capture the initiator in a status register — ID, address, and access type are stored
• Signal event to DSP interrupt controller
The software is responsible for taking corrective action to respond to the event and resetting the error status in the
memory controller. For more information on memory protection for L1D, L1P, and L2, see the C66x CorePac User
Guide in ‘‘Related Documentation from Texas Instruments’’ on page 64.
100 C66x CorePac
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