TMS320C6654 Datasheet, PDF (103/222 Pages) Texas Instruments – Fixed and Floating-Point Digital Signal Processor

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6 Device Operating Conditions
TMS320C6654
Fixed and Floating-Point Digital Signal Processor
SPRS841—March 2012
6.1 Absolute Maximum Ratings
Table 6-1
Absolute Maximum Ratings ⁽¹⁾
Over Operating Case Temperature Range (Unless Otherwise Noted)
Supply voltage range ⁽²⁾:
Input voltage (V_I) range:
Output voltage (V_O) range:
Operating case temperature range, T_C:
ESD stress voltage, V_ESD ⁽³⁾:
CVDD
CVDD1
DVDD15
DVDD18
VREFSSTL
VDDT1, VDDT2
VDDR1, VDDR2, VDDR3, VDDR4
AVDDA1, AVDDA2
VSS Ground
LVCMOS (1.8V)
DDR3
I²C
LVDS
LJCB
SerDes
LVCMOS (1.8V)
DDR3
I²C
SerDes
Commercial
Extended
HBM (human body model) ⁽⁴⁾
CDM (charged device model) ⁽⁵⁾
-0.3 V to 1.3 V
-0.3 V to 1.3 V
-0.3 V to 2.45 V
-0.3 V to 2.45 V
0.49 × DVDD15 to 0.51 × DVDD15
-0.3 V to 1.3 V
-0.3 V to 2.45 V
-0.3 V to 2.45 V
0V
-0.3 V to DVDD18+0.3 V
-0.3 V to 2.45 V
-0.3 V to 2.45 V
-0.3 V to DVDD18+0.3 V
-0.3 V to 1.3 V
-0.3 V to CVDD1+0.3 V
-0.3 V to DVDD18+0.3 V
-0.3 V to 2.45 V
-0.3 V to 2.45 V
-0.3 V to CVDD1+0.3 V
0°C to 85°C
-40°C to 100°C
±1000 V
±250 V
Overshoot/undershoot ⁽⁶⁾
Storage temperature range, T_stg:
End of Table 6-1
LVCMOS (1.8V)
DDR3
I²C
20% Overshoot/Undershoot for 20% of
Signal Duty Cycle
-65°C to 150°C
1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated
conditions for extended periods may affect device reliability.
2 All voltage values are with respect to V_SS.
3 Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
4 Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD
control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.
5 Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control
process. Pins listed as 250 V may actually have higher performance.
6 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and
maximum undershoot value would be V_SS - 0.20 × DVDD18
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Device Operating Conditions 103