TMS320C6418_11 Datasheet, PDF (75/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Peripherals Detailed Description (Device-Specific)
4 Peripherals Detailed Description (Device-Specific)
4.1 Clock PLL and Oscillator
Most of the internal C64x DSP clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock,
or bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Figure 4−1
shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.
To minimize the clock jitter, a single clean power supply should power both the C64x DSP device and the
external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input
clock timing requirements, see the input and output clocks electricals section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended
ranges of supply voltage and operating case temperature table and the input and output clocks electricals
section).
August 2004 − Revised January 2006
SPRS241D
75