TMS320C6418_11 Datasheet, PDF (118/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Reset Timing
CLKOUT4
CLKOUT6
1
RESET
2
3
AECLKIN
4
5
AECLKOUT1
AECLKOUT2
6
7
EMIF Z Group†‡
8
9
EMIF High Group†
10
11
EMIF Low Group†
12
13
High Group†
14
15
Z Group†‡
17
16
Boot and Device
Configuration Inputs§
† _{EMIF Z group consists of: AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,}
and AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, APDT., and AECLKOUT1
EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low)
High group consists of:
HRDY (when HPI is enabled, otherwise in Z group)
Z group consists of:
CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKS0, CLKS1, DR0, DR1, CLKR0, CLKR1, FSR0, FSR1,
TOUT0/HPI_EN, TOUT1/LENDIAN, GP0[7:0], HD[7:0], HD[15:8]/GP0[15:8], HD[21:16]/AXR1[5:0],
HD22/AFSX1, HD23/AFSR1, HD24/ACLKX1, HD25/ACLKR1, HD26/AHCLKR1, HD27/AHCLKX1,
HD28/AMUTE1, HD29/AMUTEIN1, HD30, HD31, HRDY (when HPI is disabled), HDS2, HDS1/ACLKR1[3],
HCS/ACLKR1[2], HAS/ACLKR1[1], HR/W/AFSR1[3], HHWIL/AFSR1[2] (16-bit HPI mode only),
HCNTL0/AFSR1[1], HCNTL1, HINT, ACLKR0, AFSR0, AHCLKR0, AMUTEIN0, AMUTE0, AXR0[5:0], SDA1,
SCL1, SDA0, SCL0, TDO, and EMU[11:0]
‡ _{If LENDIAN, BOOTMODE[1:0] (AEA[22:21] pins), AECLKIN_SEL[1:0] (AEA[20:19] pins), HPI_EN, and HD5 are actively driven, care must be}
taken to ensure no timing contention between parameters 6, 7, 14, 15, 16, and 17.
§ _{Boot and Device Configurations Inputs (during reset) include: LENDIAN, BOOTMODE[1:0] (AEA[22:21] pins), AECLKIN_SEL[1:0] (AEA[20:19]}
pins), HPI_EN, and HD5.
Figure 7−22. Reset Timing^†
118 _SPRS241D
August 2004 − Revised January 2006