TMS320C6418_11 Datasheet, PDF (124/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Inter-Integrated Circuits (I2C) Timing
Table 7−23. Switching Characteristics for I2C Timings^† (see Figure 7−29)
−500
−600
NO.
PARAMETER
STANDARD
FAST
UNIT
MODE
MODE
MIN MAX
MIN MAX
16 tc(SCL)
Cycle time, SCL
10
17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7
18
td(SDAL-SCLL)
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
4
2.5
µs
0.6
µs
0.6
µs
19 tw(SCLL)
Pulse duration, SCL low
4.7
20 tw(SCLH)
Pulse duration, SCL high
4
21 td(SDAV-SDLH) Delay time, SDA valid to SCL high
250
22 tv(SDLL-SDAV) Valid time, SDA valid after SCL low (For I2C bus devices)
0
23 tw(SDAH)
Pulse duration, SDA high between STOP and START conditions 4.7
24 tr(SDA)
Rise time, SDA
1000
25 tr(SCL)
Rise time, SCL
1000
26 tf(SDA)
Fall time, SDA
300
27 tf(SCL)
Fall time, SCL
300
28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition)
4
29 Cp
Capacitance for each I2C pin
10
† _{Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.}
1.3
0.6
100
0
1.3
20 + 0.1Cb†
20 + 0.1Cb†
20 + 0.1Cb†
20 + 0.1Cb†
0.6
µs
µs
ns
0.9 µs
µs
300 ns
300 ns
300 ns
300 ns
µs
10 pF
SDA
SCL
26
23
19
25
21
20
16
18
27
22
24
28
18
17
Stop Start
Repeated
Start
Stop
Figure 7−29. I2C Transmit Timings
124 _SPRS241D
August 2004 − Revised January 2006