TMS320C6418_11 Datasheet, PDF (26/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Peripheral Register Descriptions
2.6 Peripheral Register Descriptions
Table 2−3 through Table 2−21 identify the peripheral registers for the C6418 device by their register names,
acronyms, and hex address or hex address range. For more detailed information on the register contents, bit
names and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP
Peripherals Overview Reference Guide (literature number SPRU190).
Table 2−3. EMIFA Registers
HEX ADDRESS RANGE
0180 0000
0180 0004
0180 0008
0180 000C
0180 0010
0180 0014
0180 0018
0180 001C
0180 0020
0180 0024 − 0180 003C
0180 0040
0180 0044
0180 0048
0180 004C
0180 0050
0180 0054
0180 0058 − 0183 FFFF
ACRONYM
GBLCTL
CECTL1
CECTL0
−
CECTL2
CECTL3
SDCTL
SDTIM
SDEXT
−
PDTCTL
CESEC1
CESEC0
−
CESEC2
CESEC3
–
REGISTER NAME
EMIFA global control
EMIFA CE1 space control
EMIFA CE0 space control
Reserved
EMIFA CE2 space control
EMIFA CE3 space control
EMIFA SDRAM control
EMIFA SDRAM refresh control
EMIFA SDRAM extension
Reserved
Peripheral device transfer (PDT) control
EMIFA CE1 space secondary control
EMIFA CE0 space secondary control
Reserved
EMIFA CE2 space secondary control
EMIFA CE3 space secondary control
Reserved
COMMENTS
HEX ADDRESS RANGE
0184 0000
0184 0004 − 0184 0FFC
0184 1000
0184 1004 − 0184 1FFC
0184 2000
0184 2004
0184 2008
0184 200C
0184 2010 − 0184 3FFC
0184 4000
0184 4004
0184 4010
0184 4014
0184 4018
0184 401C
0184 4020
0184 4024
0184 4030
Table 2−4. L2 Cache Registers (C64x)
ACRONYM
CCFG
−
EDMAWEIGHT
−
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
−
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2IBAR
L2IWC
L1PIBAR
L1PIWC
L1DWIBAR
REGISTER NAME
Cache configuration register
Reserved
L2 EDMA access control register
Reserved
L2 allocation register 0
L2 allocation register 1
L2 allocation register 2
L2 allocation register 3
Reserved
L2 writeback base address register
L2 writeback word count register
L2 writeback invalidate base address register
L2 writeback invalidate word count register
L2 invalidate base address register
L2 invalidate word count register
L1P invalidate base address register
L1P invalidate word count register
L1D writeback invalidate base address register
COMMENTS
26 _SPRS241D
August 2004 − Revised January 2006