TMS320C6418_11 Datasheet, PDF (115/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

BUSREQ Timing
7.6 BUSREQ Timing
Table 7−16. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module (see Figure 7−21)
NO.
1 td(AEKO1H-ABUSRV)
PARAMETER
Delay time, AECLKOUTx high to ABUSREQ valid
−500
MIN MAX
0.6 7.1
−600
MIN MAX
1 5.5
UNIT
ns
AECLKOUTx
ABUSREQ
1
1
Figure 7−21. BUSREQ Timing for EMIFA
August 2004 − Revised January 2006
SPRS241D ¹¹⁵