TMS320C6418_11 Datasheet, PDF (110/145 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Synchronous DRAM Timing
WRITE
AECLKOUTx
ACEx
1
2
ABE[3:0]
2
4
3
BE1
BE2
BE3
BE4
AEA[22:14]
4
5
Bank
AEA[12:3]
4
5
Column
AEA13
4
5
AED[31:0]
9
9
10
D1
D2
D3
D4
AAOE/ASDRAS/ASOE†
AARE/ASDCAS/ASADS/
ASRE†
AAWE/ASDWE/ASWE†
8
8
11
11
14
14
PDT‡
† _{AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as AsDCAS, ASDWE, and ASDRAS, respectively,}
during SDRAM accesses.
‡ _{PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data}
is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 7−13.
Figure 7−13. SDRAM Write Command for EMIFA
110 _SPRS241D
August 2004 − Revised January 2006