MSP430FG6626 Datasheet, PDF (75/171 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874 – MAY 2015
6.8 JTAG Operation
6.8.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used
to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface
with MSP430 development tools and device programmers. The JTAG pin requirements are shown in
Table 6-6. For further details on interfacing to development tools and device programmers, see the
MSP430 Hardware Tools User's Guide (SLAU278). For a complete description of the features of the JTAG
interface and its implementation, see MSP430 Programming Via the JTAG Interface (SLAU320).
Table 6-6. JTAG Pin Requirements and Functions
DEVICE SIGNAL
PJ.3/TCK
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
VSS
DIRECTION
IN
IN
IN
OUT
IN
IN
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
Power supply
Ground supply
6.8.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire
interface. Spy-Bi-Wire can be used to interface with MSP430 development tools and device programmers.
The Spy-Bi-Wire interface pin requirements are shown in Table 6-7. For further details on interfacing to
development tools and device programmers, see the MSP430 Hardware Tools User's Guide (SLAU278).
For a complete description of the features of the JTAG interface and its implementation, see MSP430
Programming Via the JTAG Interface (SLAU320).
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
VSS
DIRECTION
IN
IN, OUT
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Power supply
Ground supply
6.9 Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system
by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory.
Features of the flash memory include:
• Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are
also called information memory.
• Segment A can be locked separately.
Copyright © 2015, Texas Instruments Incorporated
Detailed Description
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