MSP430FG6626 Datasheet, PDF (141/171 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874 – MAY 2015
Table 6-65. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h) (continued)
REGISTER DESCRIPTION
DMA Channel 2 source address low
DMA Channel 2 source address high
DMA Channel 2 destination address low
DMA Channel 2 destination address high
DMA Channel 2 transfer size
DMA Channel 3 control
DMA Channel 3 source address low
DMA Channel 3 source address high
DMA Channel 3 destination address low
DMA Channel 3 destination address high
DMA Channel 3 transfer size
DMA Channel 4 control
DMA Channel 4 source address low
DMA Channel 4 source address high
DMA Channel 4 destination address low
DMA Channel 4 destination address high
DMA Channel 4 transfer size
DMA Channel 5 control
DMA Channel 5 source address low
DMA Channel 5 source address high
DMA Channel 5 destination address low
DMA Channel 5 destination address high
DMA Channel 5 transfer size
REGISTER
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA3CTL
DMA3SAL
DMA3SAH
DMA3DAL
DMA3DAH
DMA3SZ
DMA4CTL
DMA4SAL
DMA4SAH
DMA4DAL
DMA4DAH
DMA4SZ
DMA5CTL
DMA5SAL
DMA5SAH
DMA5DAL
DMA5DAH
DMA5SZ
OFFSET
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
Table 6-66. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
USCI control 0
USCI control 1
USCI baud rate 0
USCI baud rate 1
USCI modulation control
USCI status
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
REGISTER
UCA0CTL0
UCA0CTL1
UCA0BR0
UCA0BR1
UCA0MCTL
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
UCA0IFG
UCA0IV
OFFSET
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
Table 6-67. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
USCI synchronous control 0
USCI synchronous control 1
REGISTER
UCB0CTL0
UCB0CTL1
OFFSET
00h
01h
Copyright © 2015, Texas Instruments Incorporated
Detailed Description 141
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