MSP430FG6626 Datasheet, PDF (140/171 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874 – MAY 2015
www.ti.com
Table 6-64. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
16-bit operand 1 – multiply
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
16 × 16 result low word
16 × 16 result high word
16 × 16 sum extension register
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
32 × 32 result 0 – least significant word
32 × 32 result 1
32 × 32 result 2
32 × 32 result 3 – most significant word
MPY32 control register 0
REGISTER
MPY
00h
MPYS
02h
MAC
04h
MACS
06h
OP2
08h
RESLO
0Ah
RESHI
0Ch
SUMEXT
0Eh
MPY32L
10h
MPY32H
12h
MPYS32L
14h
MPYS32H
16h
MAC32L
18h
MAC32H
1Ah
MACS32L
1Ch
MACS32H
1Eh
OP2L
20h
OP2H
22h
RES0
24h
RES1
26h
RES2
28h
RES3
2Ah
MPY32CTL0
2Ch
OFFSET
Table 6-65. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER DESCRIPTION
DMA General Control: DMA module control 0
DMA General Control: DMA module control 1
DMA General Control: DMA module control 2
DMA General Control: DMA module control 3
DMA General Control: DMA module control 4
DMA General Control: DMA interrupt vector
DMA Channel 0 control
DMA Channel 0 source address low
DMA Channel 0 source address high
DMA Channel 0 destination address low
DMA Channel 0 destination address high
DMA Channel 0 transfer size
DMA Channel 1 control
DMA Channel 1 source address low
DMA Channel 1 source address high
DMA Channel 1 destination address low
DMA Channel 1 destination address high
DMA Channel 1 transfer size
DMA Channel 2 control
REGISTER
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
DMA0CTL
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA2CTL
OFFSET
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
140 Detailed Description
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