TMS320DM6431_15 Datasheet, PDF (7/227 Pages) Texas Instruments – Digital Media Processor

www.ti.com
2 Device Overview
TMS320DM6431
Digital Media Processor
SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008
2.1 Device Characteristics
Table 2-1, provides an overview of the TMS320DM6431 DSP. The tables show significant features of the
DM6431 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the
package type with pin count.
Table 2-1. Characteristics of the DM6431 Processor
HARDWARE FEATURES
DDR2 Memory Controller
Asynchronous EMIF [EMIFA]
EDMA3
Timers
Peripherals
Not all peripherals pins
are available at the same
time (For more detail, see
the Device Configuration
section).
UART
I2C
McBSP
McASP
10/100 Ethernet MAC (EMAC) with
Management Data Input/Output (MDIO)
General-Purpose Input/Output Port (GPIO)
PWM
Configurable Video Port
HECC
Size (Bytes)
On-Chip Memory
Organization
MegaModule Rev ID
CPU ID + CPU Rev ID
JTAG BSDL_ID
CPU Frequency
Cycle Time
Voltage
PLL Options
BGA Package(s)
Process Technology
Product Status⁽¹⁾
Revision ID Register (MM_REVID.[15:0])
(address location: 0x0181 2000)
Control Status Register (CSR.[31:16])
JTAGID register
(address location: 0x01C4 0028)
MHz
ns
Core (V)
I/O (V)
MXI/CLKIN frequency multiplier
(27 MHz reference)
16 x 16 mm, 0.8 mm pitch
23 x 23 mm, 1.0 mm pitch
µm
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
DM6431
(16-bit bus width) [1.8 V I/O]
Asynchronous (8-bit bus width),
RAM, Flash, (8-bit NOR or 8-bit NAND)
1 (64 independent channels, 8 QDMA channels)
2 64-bit General Purpose
(configurable as 2 64-bit or 4 32-bit)
1 64-bit Watch Dog
1 (with RTS and CTS flow control)
1 (Master/Slave)
1
1 (4 serailizers)
1
Up to 111 pins
3 outputs
1 Input (VPFE)
1
128KB RAM, 64KB ROM
32K-Byte (32KB) L1 Program (L1P) RAM/Cache
(Cache up to 32KB)
64KB L1 Data (L1D) RAM/Cache
64KB Unified Mapped RAM/Cache (L2)
64KB Boot ROM
See the TMS320DM6437/35/33/31 Digital Media
Processor (DMP) [Silicon Revisions 1.1 and 1.0]
Silicon Errata (literature number SPRZ250).
See Section 6.21.1, JTAG ID (JTAGID) Register
Description(s)
300
3.33 ns (-3/-3Q/-3S)
1.2 V (-3/-3Q/-3S)
1.8 V, 3.3 V
x1 (Bypass), x14 to x30
361-Pin BGA (ZWT)
376-Pin BGA (ZDU)
0.09 µm
PD
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Submit Documentation Feedback
Device Overview
7