TMS320DM6431_15 Datasheet, PDF (66/227 Pages) Texas Instruments – Digital Media Processor

TMS320DM6431
Digital Media Processor
SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 3-6. Fixed-Multiplier Fastboot Modes (FASTBOOT = 1, AEM[2:0] = 001b)
DEVICE BOOT AND
CONFIGURATION
PINS
BOOTMODE[3:0]
BOOT DESCRIPTION⁽¹⁾
DM6431 DMP
(Master/Slave)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No Boot (Emulation Boot)
Reserved
Reserved
Reserved
EMIFA ROM FASTBOOT
with Application Image
Script (AIS)
I2C Boot
[FAST MODE]⁽³⁾
16-bit SPI Boot [McBSP0]
NAND Flash Boot
UART Boot without
Hardware Flow Control
[UART0]
EMIFA ROM FASTBOOT
without AIS
Reserved
Reserved
Reserved
Reserved
UART Boot with Hardware
Flow Control [UART0]
24-bit SPI Boot (McBSP0 +
GP[97])
Master
–
–
–
Master
Master
Master
Master
Master
Master
–
–
–
–
Master
Master
PLLC1 CLOCK SETTING AT BOOT
PLL
MODE ⁽²⁾
Bypass
–
–
–
CLKDIV1 DOMAIN
(SYSCLK1 DIVIDER)
/1
–
–
–
DEVICE
FREQUENCY
(SYSCLK1)
CLKIN
–
–
–
x20
/2
CLKIN x20 / 2
x20
/2
CLKIN x20 / 2
x20
/2
CLKIN x20 / 2
x20
/2
CLKIN x20 / 2
x20
/2
CLKIN x20 / 2
x20
/2
CLKIN x20 / 2
–
–
–
–
–
–
–
–
–
–
–
–
x20
/2
CLKIN x20 / 2
x20
/2
CLKIN x20 / 2
DSPBOOTADDR
(DEFAULT) ⁽¹⁾
0x0010 0000
–
–
–
0x0010 000
0x0010 0000
0x0010 0000
0x0010 0000
0x0010 0000
0x0010 0000
–
–
–
–
0x0010 0000
0x0010 0000
(1) For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code disables all C64x+ cache (L2, L1P, and L1D)
so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application
code must explicitly enable the cache. For more information on the bootloader, see the Using the TMS320DM643x Bootloader
Application Report (literature number SPRAAG0).
(2) The PLL MODE for Fixed-Multiplier Fastboot Modes is fixed as shown in this table; therefore, the PLLMS[2:0] configuration pins have no
effect on the PLL MODE.
(3) I2C Boot (BOOTMODE[3:0] = 0101b) is only available if the MXI/CLKIN frequency is between 21 MHz to 30 MHz. I2C Boot is not
available for MXI/CLKIN frequencies less than 21 MHz.
66
Device Configurations
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