TMS320DM6431_15 Datasheet, PDF (121/227 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6431
Digital Media Processor
SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008
6.3 Power Supplies
For more information regarding TI's power management products and suggested devices to power TI
DSPs, visit www.ti.com/dsppower.
6.3.1 Power-Supply Sequencing
The DM6431 includes one core supply (CV_DD), and two I/O supplies—DV_DD33 and DV_DDR2. To ensure
proper device operation, a specific power-up sequence must be followed. Some TI power-supply devices
include features that facilitate power sequencing—for example, Auto-Track and Slow-Start/Enable
features. For more information on TI power supplies and their features, visit www.ti.com/dsppower.
Here is a summary of the power sequencing requirements:
• The power ramp order must be DV_DD33 before DV_DDR2, and DV_DDR2 before CV_DD—meaning during
power up, the voltage at the DV_DDR2 rail should never exceed the voltage at the DV_DD33 rail. Similarly,
the voltage at the CV_DD rail should never exceed the voltage at the DV_DDR2 rail.
• From the time that power ramp begins, all power supplies (DV_DD33, DV_DDR2, CV_DD) must be stable
within 200 ms. The term "stable" means reaching the recommended operating condition (see
Section 5.2, Recommended Operating Conditions table).
6.3.2 Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DSP to minimize inductance and
resistance in the power delivery path. Additionally, when designing for high-performance applications
utilizing the DM6431 device, the PC board should include separate power planes for core, I/O, and
ground; all bypassed with high-quality low-ESL/ESR capacitors.
6.3.3 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum
distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling
capacitors, therefore physically smaller capacitors should be used while maintaining the largest available
capacitance value.
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 100 µF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
As with the selection of any component, verification of capacitor availability over the product's production
lifetime should be considered.
For more details on capacitor usage and placement, see the Implementing DDR2 PCB Layout on the
TMS320DM643x DMP DMSoC Application Report (literature number SPRAAL6).
6.3.4 DM6431 Power and Clock Domains
The DM6431 includes one single power domain — the "Always On" power domain. The "Always On"
power domain is always on when the chip is on. The "Always On" domain is powered by the CV_DD pins of
the DM6431. All DM6431 modules lie within the "Always On" power domain. Table 6-1 provides a listing of
the DM6431 clock domains.
One primary reference clock is required for the DM6431 device. It can be either a crystal input or driven by
external oscillators. A 27-MHz crystal is recommended for the PLLs, which generate the internal clocks for
the digital media processor (DMP), peripherals, and EDMA3.
The DM6431 architecture is divided into the power and clock domains shown in Table 6-1. Table 6-2 and
Table 6-3 further discuss the clock domains and their ratios. Figure 6-4 shows the Clock Domain block
diagram.
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Peripheral Information and Electrical Specifications 121