TMS320DM6431_15 Datasheet, PDF (167/227 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6431
Digital Media Processor
SPRS342C – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-27. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller⁽¹⁾⁽²⁾(see Figure 6-18)
NO.
PARAMETER
-3/-3Q/-3S
MIN MAX
1
t_{c(DDR_CLK)}
Cycle time, DDR_CLK
7.5
8
(1) DDR_CLK cycle time = 2 x PLL2 _SYSCLK1 cycle time.
(2) The PLL2 Controller must be programmed such that the resulting DDR_CLK clock frequency is within the specified range.
UNIT
ns
1
DDR_CLK
Figure 6-18. DDR2 Memory Controller Clock Timing
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Peripheral Information and Electrical Specifications 167