TLK2711JRZQE Datasheet, PDF (7/27 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2711
1.6 TO 2.7 GBPS TRANSCEIVER
NAME
VDD
VDDA
TERMINAL
NO.
GQE
RCP
C5, D5,
E5, F5,
G5, C6,
D6, E6,
F6, G6,
C7, D7,
E7, F7,
G7, E8
1, 9, 23,
38, 48
H5
55, 57
Terminal Functions (Continued)
SLLS501 – SEPTEMBER 2001
I/O
DESCRIPTION
I/O
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver
and transmitter
detailed description
transmit interface
The transmitter portion registers valid incoming 16-bit wide data (TXD[0:15]) on the rising edge of the TXCLK.
The data is then 8-bit/10-bit encoded, serialized, and transmitted sequentially over the differential high-speed
I/O channel. The clock multiplier multiplies the reference clock (TXCLK) by a factor of 10 times, creating a bit
clock. This internal bit clock is fed to the parallel-to-serial shift register which transmits data on both the rising
and falling edges of the bit clock, providing a serial data rate that is 20 times the reference clock. Data is
transmitted LSB (TXD0) first.
transmit data bus
The transmit bus interface accepts 16-bit single-ended TTL parallel data at the TXD[0:15] terminals. Data and
K-code control is valid on the rising edge of the TXCLK. The TXCLK is used as the word clock. The data, K-code,
and clock signals must be properly aligned as shown in Figure 2. Detailed timing information can be found in
the electrical characteristics table.
TXCLK
TXD[0–15]
tsu
th
TKLSB, TKMSB
Figure 2. Transmit Timing Waveform
transmission latency
The data transmission latency of the TLK2711 is defined as the delay from the initial 16-bit word load to the serial
transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon process
variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly.
The minimum transmit latency t_{d(Tx latency)} is 34 bit times; the maximum is 38 bit times. Figure 3 illustrates the
timing relationship between the transmit data bus, the TXCLK, and the serial transmit terminals.
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