TLK2711JRZQE Datasheet, PDF (5/27 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2711
1.6 TO 2.7 GBPS TRANSCEIVER
NAME
ENABLE
TERMINAL
NO.
GQE
RCP
A5
24
GND
GNDA
A1, J1,
D3, E3,
F3, G3,
C4, D4,
E4, F4,
G4, A9, J9
H4, H6
5, 13, 18,
28, 33, 43
52, 58, 61
LCKREFN
B5
25
LOOPEN
B6
21
PRE
J5
56
PRBSEN
A4
26
RKLSB
A3
29
RKMSB
B3
30
RXCLK
E2
RX_CLK
41
† _{Internal 10k pullup}
‡ _{Internal 10k pulldown}
Terminal Functions
SLLS501 – SEPTEMBER 2001
I/O
DESCRIPTION
I^† Device enable. When this terminal is held low, the device is placed in power-down mode. Only
the signal detect circuit on the serial receive pair is active. When asserted high while the
device is in power-down mode, the transceiver goes into power-on reset before beginning
normal operation.
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and
TX.
I^† Lock to reference. When LCKREFN is low, the receiver clock is frequency locked to TXCLK.
This places the device in a transmit only mode since the receiver is not tracking the data.
When LCKREFN is asserted low, the receive data bus terminals, RXD[0:15], RXCLK and
RKLSB, RKMSB are in a high-impedance state.
When LCKREFN is deasserted high, the receiver is locked to the received data stream.
I^‡ Loop enable. When LOOPEN is active high, the internal loop-back path is activated. The
transmitted serial data is directly routed internally to the inputs of the receiver. This provides
a self-test capability in conjunction with the protocol device. The TXP and TXN outputs are
held in a high-impedance state during the loop-back test. LOOPEN is held low during standard
operational state with external serial outputs and inputs active.
I^‡ Preemphasis control. Selects the amount of preemphasis to be added to the high speed serial
output drivers. Left low or unconnected, 5% preemphasis is added. Pulled high, 20%
preemphasis is added.
I^‡ PRBS test enable. When asserted high results of pseudo random bit stream (PRBS) tests can
be monitored on the RKLSB terminal. A high on RKLSB indicates that valid PRBS is being
received.
O K-Code indicator/PRBS test results. When RKLSB is asserted high, an 8-bit/10-bit K code
was received and is indicated by data bits RXD0–RXD7. When RKLSB is asserted low an
8-bit/10-bit D code is received and is presented on data bits RXD0–RXD7.
When PRBSEN is asserted high this pin is used to indicate status of the PRBS test results
(high = pass).
O K-code indicator. When RKMSB is asserted high an 8-bit/10-bit K code was received and is
indicated by data bits RXD8 –RXD15. When RKMSB is asserted low an 8-bit/10-bit D code
was received and is presented on data bits RXD8 – RXD15. If the differential signal on RXN
and RXP drops below 200 mV, then RXD [0:15], RKLSB, and RKMSB are all asserted high.
O Recovered clock. Output clock that is synchronized to RXD [0..9], RKLSB, and RKMSB.
RXCLK is the recovered serial data rate clock divided by 20. RXCLK is held low during
power-on reset.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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