TLK2711JRZQE Datasheet, PDF (14/27 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2711
1.6 TO 2.7 GBPS TRANSCEIVER
SLLS501 – SEPTEMBER 2001
reference clock (TXCLK) timing requirements over recommended operating conditions (unless
otherwise noted)
PARAMETER
Frequency
Frequency
Frequency tolerance
Duty cycle
Jitter
TEST CONDITIONS
Minimum data rate
Maximum data rate
Peak-to-peak
MIN
Typ –0.01%
Typ –0.01%
– 100
40%
TYP MAX
80 Typ+0.01%
135 Typ+0.01%
100
50%
60%
40
UNIT
MHz
MHz
ppm
ps
TTL input electrical characteristics over recommended operating conditions (unless otherwise
noted), TTL signals: TXDO–TXD15, TXCLK, LOOPEN, LCKREFN, ENABLE, PRBS_EN, TKLSB,
TKMSB, PRE
PARAMETER
VIH High-level input voltage
VIL Low-level input voltage
IIH Input high current
IIL Input low current
CI Receiver input capacitance
tr
Rise time, TXCLK, TKMSB, TKLSB, TXD[0..15]
tf
Fall time, TXCLK, TKMSB, TKLSB, TXD[0..15]
tsu TXD[0..15], TKMSB, TKLSB setup to ↑ TXCLK
th
TXD, TKMSB, TKLSB hold to ↑ TXCLK
TEST CONDITIONS
See Figure 7
See Figure 7
VDD = MAX, VIN = 2 V
VDD = MAX, VIN = 0.4 V
0.7 V to 1.9 V, C = 5 pF, SeeFigure 7
1.9 V to 0.7 V, C = 5 pF, See Figure 7
See Figure 7
See Figure 7
MIN NOM
1.7
– 40
1
1
1.5
0.4
MAX
3.6
0.80
40
4
UNIT
V
V
µA
µA
pF
ns
ns
ns
ns
TXCLK
TKLSB, TKMSB,
TXD[0–15]
tr
tf
tsu
tr
tf
th
Figure 7. TTL Data Input Valid Levels for AC Measurements
3.6 V
2.0 V
0.8 V
0V
3.6 V
2.0 V
0.8 V
0V
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