TLK2711JRZQE Datasheet, PDF (12/27 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2711
1.6 TO 2.7 GBPS TRANSCEIVER
SLLS501 – SEPTEMBER 2001
detailed description (continued)
reference clock input
The reference clock (TXCLK) is an external input clock that synchronizes the transmitter interface. The
reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal
serialization bit clock is frequency-locked to the reference clock and used to clock out the serial transmit data
on both its rising and falling edges, providing a serial data rate that is 20 times the reference clock.
operating frequency range
The TLK2711 can operate at a serial data rate from 1.6 Gbps to 2.7 Gbps. To achieve these serial rates, TXCLK
must be within 80 MHz to 135 MHz. The TXCLK must be within ±100 PPM of the desired parallel data rate clock.
testability
The TLK2711 has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed
testing of the transmit/receive portions of the circuitry. The enable terminal allows for all circuitry to be disabled
so that a quiescent current test can be performed. The PRBS function allows for BIST (built-in self-test).
loopback testing
The transceiver can provide a self-test function by enabling (LOOPEN) the internal loop-back path. Enabling
this terminal causes serial-transmitted data to be routed internally to the receiver. The parallel data output can
be compared to the parallel input data for functional verification. (The external differential output is held in a
high-impedance state during the loopback testing.)
built-in self-test (BIST)
The TLK2711 has a BIST function. By combining PRBS with loopback, an effective self-test of all the circuitry
running at full speed can be realized. The successful completion of the BIST is reported on the RKLSB terminal.
power-on reset
Upon application of minimum valid power, the TLK2711 generates a power-on reset. During the power-on reset
the RXD[0..15], RKLSB, and RKMSB signal terminals go to a high-impedance state. The RXCLK is held low.
The length of the power-on reset cycle is dependent upon the TXCLK frequency, but is less than 1 ms.
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