TLK2711JRZQE Datasheet, PDF (10/27 Pages) Texas Instruments – 1.6 TO 2.7 GBPS TRANSCEIVER

TLK2711
1.6 TO 2.7 GBPS TRANSCEIVER
SLLS501 – SEPTEMBER 2001
detailed description (continued)
data reception latency
The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output
in the aligned parallel word. The receive latency is fixed once the link is established. However, due to silicon
process variations and implementation variables such as supply voltage and temperature, the exact delay
varies slightly. The minimum receive latency t_{d(Rx latency)} is 76 bit times; the maximum is 107 bit times. Figure
6 illustrates the timing relationship between the serial receive terminals, the recovered word clock (RXCLK),
and the receive data bus.
20-Bit Encoded Word
RXN,
RXP
RXD[0–15]
t_{d(Rx latency)}
16-Bit Decoded Word
RXCLK
Figure 6. Receiver Latency
serial-to-parallel
Serial data is received on the RXP and RXN terminals. The interpolator and clock recovery circuit locks to the
data stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock. The
recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel
shift registers. The 10-bit wide parallel data is then multiplexed and fed into two separate 8-bit/10-bit decoders
where the data is then synchronized to the incoming data stream word boundary by detection of the comma
8-bit/10-bit synchronization pattern.
comma detect and 8-bit/10-bit decoding
The TLK2711 has two parallel 8-bit/10-bit decode circuits. Each 8-bit/10-bit decoder converts 10 bit encoded
data (half of the 20-bit received word) back into 8 bits. The comma detect circuit is designed to provide for byte
synchronization to an 8-bit/10-bit transmission code. When parallel data is clocked into a parallel to serial
converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data.
When the serial data is received and converted to parallel format again, a method is needed to recognize the
byte boundary. Generally this is accomplished through the use of a synchronization pattern. This is generally
a unique pattern of 1’s and 0’s that either cannot occur as part of valid data or is a pattern that repeats at defined
intervals. The 8-bit/10-bit encoding contains a character called the comma (b0011111 or b1100000), which is
used by the comma detect circuit on the TLK2711 to align the received serial data back to its original byte
boundary. The decoder detects the comma, generating a synchronization signal aligning the data to their 10-bit
boundaries for decoding; the comma is mapped into the LSB. The decoder then converts the data back into 8-bit
data. The output from the two decoders is latched into the 16-bit register synchronized to the recovered parallel
data clock (RXCLK) and output valid on the rising edge of the RXCLK.
NOTE:
The TLK2711 only achieves byte alignment on the 0011111 comma.
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