TLC5971_15 Datasheet, PDF (7/45 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum, PWM, RGB, LED Driver

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TLC5971
SBVS146D – AUGUST 2010 – REVISED DECEMBER 2015
Electrical Characteristics (continued)
At T_A = –40°C to +85°C, V_CC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, VLED = 5 V, and C_VREG = 1 µF, unless otherwise
noted. Typical values are at T_A = 25°C and VCC = 12 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ΔI_OLC3
T_TSD
T_HYS
V_IREF
V_REG
ΔV_REG
ΔV_REG1
V_STR
V_HYS
Load regulation of constant-current output,
OUTXn ⁽⁴⁾
Thermal shutdown temperature
Thermal shutdown hysteresis
Reference voltage output, IREF
Linear regulator output voltage, VREG
Line regulation of linear regulator, VREG
Load regulation of linear regulator, VREG
Undervoltage lockout release, VREG
Undervoltage lockout hysteresis, VREG
All OUTn on, BCX = 7Fh, V_OUTXn = V_OUTfix = 1 V,
R_IREF = 0.82 kΩ (I_OLCMax = 60 mA)
Junction temperature⁽⁵⁾
Junction temperature⁽⁵⁾
R_IREF = 0.82 kΩ
VCC = 6 V to 17 V, IREG = 0 mA to –25 mA
VCC = 6 V to 17 V, IREG = 0 mA
VCC = 12 V, IREG = 0 mA to –25 mA
–3
±1
3
%/V
150
165
180
°C
5
10
20
°C
1.18
1.21
1.24
V
3.1
3.3
3.5
V
90
mV
120
mV
2.5
2.7
2.9
V
300
400
500
mV
(4)
Load regulation is calculated by Equation 5:
D (%/V) =
(I_OLCXn at V_OUTXn = 3 V) - (I_OLCXn at V_OUTXn = 1 V)
(I_OLCXn at V_OUTXn = 1 V)
100
´
3V-1V
where
(a) X = R/G/B,
(b) n = 0-3.
(5)
(5) Not tested, specified by design.
6.6 Switching Characteristics
At T_A = –40°C to +85°C, V_CC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, C_VREG = 1 µF, C_L = 15 pF, R_L = 68 Ω, and VLED =
5 V, unless otherwise noted. Typical values are at T_A = 25°C and VCC = 12 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
t_R0
t_R1
t_F0
t_F1
t_D0
t_D1
t_D2 ⁽¹⁾
t_D3
Rise time, SDTO/SCKO
Rise time, OUTXn
Fall time, SDTO/SCKO
Fall time, OUTXn
BCX = 7Fh
BCX = 7Fh
SCKI↑ to SDTO↑↓
SCKI↑ to SCKO↑
SCKO↑ to SDTO↑↓
SCKI↑ to OUTRn↑↓, BLANK = 0, BCXn =
7Fh, OUTTMG = 1
Or SCKI↓ to OUTRn↑↓, BLANK = 0,
BCXn = 7Fh, OUTTMG = 0
3
5
3
15
10
25
5
15
5
10
10
25
10 ns
15 ns
10 ns
25 ns
60 ns
40 ns
20 ns
60 ns
Propagation delay
t_D4
SCKI↑ to OUTGn↑↓, BLANK = 0, BCXn
= 7Fh, OUTTMG = 1
Or SCKI↓ to OUTGn↑↓, BLANK = 0,
BCXn = 7Fh, OUTTMG = 0
25
50
90 ns
SCKI↑ to OUTBn↑↓, BLANK = 0, BCXn =
t_D5
7Fh, OUTTMG = 1
Or SCKI↓ to OUTBn↑↓, BLANK = 0,
40
75
120 ns
BCXn = 7Fh, OUTTMG = 0
t_D6 ⁽²⁾
Last SCKI↑ to internal latch pulse
genaration
8/f_OSC
16384/f_OSC
s
t_W(SCKO) Shift clock output one pulse width SCKO↑ to SCKO↓
f_OSC
Internal oscillator frequency
12
25
6
10
35 ns
12 MHz
(1) The propagation delays are calculated by t_D2 = t_D0 – t_D1.
(2) The generation timing of the internal latch pulse changes depending on the SCKI clock frequency; see the Internal Latch Pulse
Generation Timing section.
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