TLC5971_15 Datasheet, PDF (25/45 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum, PWM, RGB, LED Driver

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TLC5971
SBVS146D – AUGUST 2010 – REVISED DECEMBER 2015
8.5.5 Internal Latch Pulse Generation Timing
The internal latch pulse is generated when the SCKI rising edge does not change for 8x the period between the
last SCKI rising edge and the second to last SCKI rising edge if the data of the six MSBs in the 244-bit shift
register are the command code 25h. The generation timing changes as a result of the SCKI frequency with the
time range between 16384 times the internal oscillator period (2.74 ms), maximum, and 8x the internal oscillator
period (666 ns), minimum. Figure 30 shows the internal latch pulse generation timing.
The internal latch pulse is generated when the SCKI rising edge is not input during 8 times of
Period A if the 6-bit data of the MSB-side in the 244-bit shift register is the command code 25h.
SCKI
Latch Pulse
(Internal)
224-Bit Shift
Register Data
(Internal)
1
2
3
4¼
N-3 N-2 N-1 N
Period A
Write command 25h + 218-bit data.
The next SCKI clock should start after 8 or more
clock periods (1.34 ms, min) of the internal clock
from the internal latch pulse generation timing.
218-Bit
Data Latch
(Internal)
218-bit data are copied from shift register
when the internal latch is generated.
Figure 30. Data Latch Pulse Generation Timing
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