TLC5971_15 Datasheet, PDF (29/45 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum, PWM, RGB, LED Driver

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TLC5971
SBVS146D – AUGUST 2010 – REVISED DECEMBER 2015
VLED Power
Shift Data From
Controller (SDTI)
Shift Clock From
Controller (SCKI)
MSB
LSB
224-Bit Packet
for Nth TLC5971
for
N-1st
MSB
224 Shift Clocks
MSB
LSB
for
224-Bit Packet
2nd
for 1st TLC5971
LSB
224 Shift Clocks
The next shift clock should start after 1.34 ms
or more from the internal latch pulse generation timing.
Low
MSB
224-Bit Packet
for Nth TLC5971
65536 Shift Clocks as GS Clock
224 Shift
Clocks
Latch Pulse
(Internal)
OUTXn
OUTXn is controlled via the PWM
synchronized with SCKI.
The time that generates the internal latch pulse is 8x the period between the last
SCLK rising edge and the second to last SCLK rising edge. The time changes
depending on the period of the shift clock within the range of 2.74 ms to 666 ns.
Figure 35. Data Packet and Display Start/Update Timing 2 (External Clock Mode)
There is another control procedure that is recommended for a long chain of cascaded devices. The data and
clock timings are shown in Figure 3 and Figure 36. When 256 TLC5971 units are cascaded, use the following
procedure:
1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet MSB-first for the 256th TLC5971 using the SDTI and SCKI signals. The
EXTCLK bit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 so
that the PWM control does not repeat, the TMGRST bit should be set to 1 to reset the PWM control timing
with the internal latch pulse, and BLANK must be set to 0 to start the PWM control.
3. Repeat the data write sequence for all TLC5971s. The total shift clock count (SCKI) is 57344 (224 × 256).
After all device data are written, stop the SCKI signal at a high or low level for eight or more periods between
the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift
resister are copied to the 218-bit data latch in all devices.
4. To control the PWM, send 8192 SCKI clock periods with SDTI low after 1.34 µs or more from step 3 (or step
7). These 8192 clock periods are used for the OUTXn PWM control.
5. Write the new 224-bit data packets to the 256th to first TLC5971s for the next display with 256 × 224 SCKI
clock for a total of 57344 clocks. The PWM control for OUTXn remains synchronized with the SCKI clock and
one display period is finished with a total of 65536 SCKI clocks. The SCKI clock signal is therefore used for
PWM control and, at the same time, to write data into the shift registers of all cascaded parts.
6. Stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge and
the second to last SCKI rising edge. Then the 218-bit LSBs in the 224-bit shift resister are copied to the 218-
bit data latch in all devices.
7. Repeat step 4 to step 6 for the next display periods.
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