TLC5971_15 Datasheet, PDF (27/45 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum, PWM, RGB, LED Driver

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TLC5971
SBVS146D – AUGUST 2010 – REVISED DECEMBER 2015
9.2.2.2 Data Input Sequence
224-bit data packets are sent through single-wire interface for the PWM control of three output channels. Select
the BC data, FC data and write the GS data to the register following the signal timing.
9.2.2.3 How to Control the TLC5971
To set each function mode, BC color, GS output, 6-bit write command, 5-bit FC data, 21-bit BC data for each
color group, and 192-bit GS data for OUTXn, a total number of 224 bits must be written into the device.
Figure 32 shows the 224-bit data packet configuration.
When N units of the TLC5971 are cascaded (as shown in Figure 33), N × 224 bits must be written from the
controller into the first device to control all devices. The number of cascaded devices is not limited as long as the
proper voltage is supplied to the device at VCC. The packets for all devices must be written again whenever the
data in one packet is changed.
MSB
Write
Command
(6 bits, 25h)
Function
Control
(5 bits)
BC for
BLUE
(7 bits)
BC for
GREEN
(7 bits)
BC for
RED
(7 Bits)
GS for
OUTB3
(16 Bits)
GS for
OUTG3
(16 Bits)
GS for
OUTR3
(16 Bits)
16 Bits
´6
GS for
OUTB0
(16 Bits)
GS for
OUTG0
(16 Bits)
LSB
GS for
OUTR0
(16 Bits)
Figure 32. 224-Bit Data Packet Configuration
VLED
3.3 V
Controller
DATA
CLK
GND
¼
VCC
SDTI
SDTO
SCKI
SCKO
IREF
VREF
1st
TLC5971
GND
¼
VCC
SDTI
SDTO
SCKI
SCKO
IREF
VREF
2nd
TLC5971
GND
¼
VCC
SDTI
SDTO
SCKI
SCKO
IREF
VREF
N-1st
TLC5971
GND
¼
VCC
SDTI
SDTO
SCKI
SCKO
IREF
VREF
Nth
TLC5971
GND
Figure 33. Cascading Connection of N TLC5971 Units
9.2.2.3.1 Data Write and PWM Control with Internal Grayscale Clock Mode
When the EXTCLK bit is 0, the internal oscillator clock is used for PWM control of OUTXn (X = R/G/B and n = 0-
3) as the GS reference clock. This mode is ideal for illumination applications that change the display image at
low frequencies. The data and clock timing is shown in Figure 3 and Figure 34. A writing procedure for the
function setting and display control follows:
1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet (with MSB bit first) for the Nth TLC5971 using the SDTI and SCKI signals. The
first six bits of the 224-bit data packet are used as the write command. The write command must be 25h
(100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch.
The EXTCLK bit must be set to 0 for the internal oscillator mode. Also, the DSPRPT bit should be set to 1 to
repeat the PWM timing control and BLANK set to 0 to start the PWM control.
3. Write the 224-bit data packet for the (N – 1) TLC5971 without delay after step 2.
4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is now 224 ×
N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the last
SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are
copied to the 218-bit data latch in all devices and the PWM control is started or updated at the same time.
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