TLC5971_15 Datasheet, PDF (30/45 Pages) Texas Instruments – 12-Channel, 16-Bit, Enhanced Spectrum, PWM, RGB, LED Driver

TLC5971
SBVS146D – AUGUST 2010 – REVISED DECEMBER 2015
www.ti.com
VLED Power
Shift Data From
Controller (SDTI)
Shift Clock From
Controller (SCKI)
Latch Pulse
(Internal)
MSB
LSB
224-Bit Packet for for
256th TLC5971 255th
MSB
The next shift clock should start after 1.34 ms or more from the internal latch pulse generation timing.
MSB
LSB
for
224-Bit Packet
2nd
for 1st TLC5971
LSB
Timing clock for 1st display.
Timing clock for 1st display and
2nd display data write.
Low
256 ´ 224-Bit Packet for
256th TLC5971
Low
224 Shift Clocks
224 Shift Clocks
224 ´ 256 = 57344 Clocks
8192
Shift Clocks
57344 (256 ´ 224)
Shift Clocks
65536 Clocks
Shift Clock
for 2nd Display
65536 Clocks
OUTXn
OFF
OUTXn is controlled via the PWM synchronized
with SCKI for 1st dis playperiod.
OFF
2nd Display
Period
The time is 8 periods between the last SCLK rising edge and the second to last SCLK rising edge.
The wait time changes between 2.74 ms and 666 ns, depending on the period of the shift clock.
Figure 36. Data Packet and Display Start/Update Timing 3
(External Clock Mode With 256 Cascaded Devices)
9.2.3 Application Curve
Figure 37. Output Waveform With GS Data Latch Input
30
Submit Documentation Feedback
Product Folder Links: TLC5971
Copyright © 2010–2015, Texas Instruments Incorporated