TLC59116-Q1 Datasheet, PDF (7/39 Pages) Texas Instruments – 16-Channel Constant-Current LED Sink Driver

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TLC59116-Q1
SLDS223A – MARCH 2016 – REVISED MARCH 2016
7.6 Timing Requirements
T_A = –40°C to +105°C
I²C INTERFACE
f_SCL
SCL clock frequency ⁽¹⁾
t_BUF
I²C Bus free time between Stop and Start
conditions
t_HD;STA
Hold time (repeated) Start condition
t_SU;STA
Set-up time for a repeated Start condition
t_SU;STO
Set-up time for Stop condition
t_HD;DAT
Data hold time
t_VD;ACK
Data valid acknowledge time ⁽²⁾
t_VD;DAT
Data valid time ⁽³⁾
t_SU;DAT
Data set-up time
t_LOW
Low period of SCL clock
t_HIGH
t_f
High period of SCL clock
Fall time of both SDA and SCL signals ^{(4) (5)}
t_r
Rise time of both SDA and SCL signals
I²C BUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
STANDARD MODE
FAST MODE
FAST MODE PLUS
MIN
0
0
0
4.7
1.3
0.5
4
0.6
0.26
4.7
0.6
0.26
4
0.6
0.26
0
0
0
0.3
0.1
0.05
0.3
0.1
0.05
250
100
50
4.7
1.3
0.5
4
0.6
0.26
20+0.1C_b ⁽⁶⁾
20+0.1C_b ⁽⁶⁾
MAX UNIT
100
400 kHz
1000
μs
μs
μs
μs
ns
3.45
0.9 μs
0.45
3.45
0.9 μs
0.45
ns
μs
μs
300
300 ns
120
1000
300 ns
120
(1) The TLC59116-Q1 does not have a self timeout on the I²C Bus. The Master can issue a reset if needed.
(2) t_VD;ACK = time for ACK signal from SCL low to SDA (out) low.
(3) t_VD;DAT = minimum time for SDA data out to be valid following SCL low.
(4) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_IL of the SCL signal) in order to
bridge the undefined region of the SCL falling edge.
(5) The maximum t_f for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t_f) for the SDA output stage is specified
at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t_f.
(6) C_b = Total capacitance of one bus line in pF
Copyright © 2016, Texas Instruments Incorporated
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