TLC59116-Q1 Datasheet, PDF (16/39 Pages) Texas Instruments – 16-Channel Constant-Current LED Sink Driver

TLC59116-Q1
SLDS223A – MARCH 2016 – REVISED MARCH 2016
Programming (continued)
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SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 10. Bit Transfer
9.5.1.2 Start and Stop Conditions
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the Stop condition (P) (see Figure 11).
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 11. Start and Stop Conditions
9.5.1.3 Acknowledge
The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on
the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. See
Figure 12.
A slave receiver that is addressed must generate an acknowledge after the reception of each byte. Also a master
must generate an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and
hold time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable
the master to generate a Stop condition. See Figure 13.
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