DS90CR481_15 Datasheet, PDF (7/25 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

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DS90CR481, DS90CR482
AC Timing Diagrams
SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013
(1) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Figure 1. “Worst Case” Test Pattern
Figure 2. DS90CR481 (Transmitter) LVDS Output Load and Transition Times
Figure 3. DS90CR482 (Receiver) CMOS/TTL Output Load and Transition Times
Figure 4. DS90CR481 (Transmitter) Input Clock Transition Time
Figure 5. DS90CR481 (Transmitter) Setup/Hold and High/Low Times
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