DS90CR481_15 Datasheet, PDF (5/25 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

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DS90CR481, DS90CR482
SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
LLHT
LVDS Low-to-High Transition Time, (Figure 2),
0.14
PRE = 0.75V (disabled)
LVDS Low-to-High Transition Time, (Figure 2),
0.11
PRE = Vcc (max)
LHLT
LVDS High-to-Low Transition Time, (Figure 2),
0.16
PRE = 0.75V (disabled)
LVDS High-to-Low Transition Time, (Figure 2),
0.11
PRE = Vcc (max)
TBIT
Transmitter Bit Width
f = 66 MHz,
112MHz
1/7 TCIP
TPPOS Transmitter Pulse Positions - Normalized f = 65 to 112
− 200
0
MHz
TJCC
Tranmitter Jitter - Cycle-to-Cycle
100
TCCS
TxOUT Channel to Channel Skew
40
TSTC
TxIN Setup to TxCLK IN, (Figure 5)
2.5
THTC
TxIN Hold to TxCLK IN, (Figure 5)
0
TPDL
Transmitter Propagation Delay - Latency, (Figure 7)
1.5(TCIP)+3.72 1.5(TCIP)+4.4
TPLLS Transmitter Phase Lock Loop Set, (Figure 9)
TPDD
Transmitter Powerdown Delay, (Figure 11)
Max
Units
0.7
ns
0.6
ns
0.8
ns
0.7
ns
ns
+200
ps
ps
ps
ns
ns
1.5(TCIP)+6.24
ns
10
ms
100
ns
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
CLHT
CMOS/TTL Low-to-High Transition Time, Rx data out,
(Figure 3)
CMOS/TTL Low-to-High Transition Time, Rx clock out,
(Figure 3)
CHLT
CMOS/TTL High-to-Low Transition Time, Rx data out,
(Figure 3)
CMOS/TTL High-to-Low Transition Time, Rx clock out,
(Figure 3)
RCOP
RxCLK OUT Period, (Figure 6)
8.928
T
RCOH
RxCLK OUT High Time, (Figure 6), ⁽¹⁾ f = 112 MHz
3.5
f = 66 MHz
6.0
RCOL
RxCLK OUT Low Time, (Figure 6), ⁽¹⁾ f = 112 MHz
3.5
f = 66 MHz
6.0
RSRC
RxOUT Setup to RxCLK
OUT,(Figure 6)
f = 112 MHz
2.4
f = 66 MHz
3.6
RHRC
RxOUT Hold to RxCLK OUT,
f = 112 MHz
3.4
(Figure 6), ⁽¹⁾
f = 66 MHz
6.0
RPDL
Receiver Propagation Delay - Latency, (Figure 8)
3(TCIP)+4.0
3(TCIP)+4.8
RPLLS Receiver Phase Lock Loop Set, (Figure 10)
RPDD
Receiver Powerdown Delay, (Figure 12)
Max
2.0
1.0
2.0
1.0
15.38
3(TCIP)+6.5
10
1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges.
This parameter is functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts
have been bench tested to verify functional performance.
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