DS90CR481_15 Datasheet, PDF (16/25 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

DS90CR481, DS90CR482
SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013
www.ti.com
Table 3. DS90CR481 Pin Descriptions—Channel Link Transmitter
Pin Name
TxIN
TxOUTP
TxOUTM
TxCLKIN
TxCLKP
TxCLKM
PD
PLLSEL
PRE
DS_OPT
BAL
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
NC
I/O
I
TTL level input. ⁽¹⁾
Description
O Positive LVDS differential data output.
O Negative LVDS differential data output.
I TTL level clock input. The rising edge acts as data strobe.
O Positive LVDS differential clock output.
O Negative LVDS differential clock output.
I TTL level input. Assertion (low input) tri-states the outputs, ensuring low current at power down. ⁽¹⁾
I
PLL range select. This pin must be tied to V_CC. NC or tied to Ground is reserved for future use. ⁽¹⁾
I Pre-emphasis “level” select. Pre-emphasis is active when input is tied to V_CC through external pull-up
resistor. Resistor value determines Pre-emphasis level (See APPLICATIONS INFORMATION Section). For
normal LVDS drive level (No Pre-emphasis) leave this pin open (do not tie to ground).
I Cable Deskew performed when TTL level input is low. No TxIN data is sampled during Deskew. To
perform Deskew function, input must be held low for a minimum of 4 clock cycles. The Deskew operation is
normally conducted after the TX and RX PLLs have locked. It should also be conducted after a system
reset, or a reconfiguration event. It must be peformed at least once when "DESKEW" is enabled. ⁽²⁾
I TTL level input. This pin was previously labeled as V_CC, which enabled the DC Balance function. But when
tied low or left open, the DC Balance function is disabled. Please refer to (Figure 15 Figure 16) for LVDS
data bit mapping respectively. ⁽²⁾, ⁽³⁾
I Power supply pins for TTL inputs and digital circuitry. Bypass not required on Pins 20 and 21.
I Ground pins for TTL inputs and digital circuitry.
I Power supply pin for PLL circuitry.
I Ground pins for PLL circuitry.
I Power supply pin for LVDS outputs.
I Ground pins for LVDS outputs.
No Connect. Make NO Connection to these pins - leave open.
(1) Inputs default to “low” when left open due to internal pull-down resistor.
(2) Inputs default to “low” when left open due to internal pull-down resistor.
(3) The DS90CR482 is design to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90CR481 and
deserialize the LVDS data according to the define bit mapping.
Pin Name
RxINP
RxINM
RxOUT
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
DESKEW
PD
V_CC
GND
PLLV_CC
PLLGND
Table 4. DS90CR482 Pin Descriptions—Channel Link Receiver⁽¹⁾
I/O
Description
I
Positive LVDS differential data inputs.
I
Negative LVDS differential data inputs.
O
TTL level data outputs. In PowerDown (PD = Low) mode, receiver outputs are forced to a Low
state.
I
Positive LVDS differential clock input.
I
Negative LVDS differential clock input.
O
TTL level clock output. The rising edge acts as data strobe.
I
PLL range select. This pin must be tied to V_CC. NC or tied to Ground is reserved for future use. ⁽²⁾
I
Deskew / Oversampling “on/off” select. When using the Deskew / Oversample feature this pin
must be tied to V_CC. Tieing this pin to ground disables this feature. ⁽²⁾ Deskew is only supported in
the DC Balance mode.
I
TTL level input. When asserted (low input) the receiver outputs are Low. ⁽²⁾
I
Power supply pins for TTL outputs and digital circuitry. Bypass not required on Pins 6 and 77.
I
Ground pins for TTL outputs and digital circuitry.
I
Power supply for PLL circuitry.
I
Ground pin for PLL circuitry.
(1) These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under
test conditions receiver inputs will be in a HIGH state. If the cable interconnect (media) are disconnected which results in
floating/terminated inputs, the outputs will remain in the last valid state.
(2) Inputs default to “low” when left open due to internal pull-down resistor.
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