DS90CR481_15 Datasheet, PDF (10/25 Pages) Texas Instruments – 48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz

DS90CR481, DS90CR482
SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
■ Cable Skew—typically 10 ps–40 ps per foot, media dependent
■ Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
■ ISI is dependent on interconnect length; may be zero
See APPLICATIONS INFORMATION section for more details.
Figure 13. Receiver Skew Margin (RSKM) for Chipset without DESKEW
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
■ d= Tppos—Transmitter output pulse position (min and max)
■ f= Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate)
■ m= extra margin - assigned to ISI in long cable applications
See APPLICATIONS INFORMATION section for more details.
Figure 14. Receiver Skew Margin (RSKMD) for Chipset with DESKEW
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